Laatste wijzigingen

[matthijs/master-project/haskell-symposium-talk.git] / reducer.lhs

diff --git a/reducer.lhs b/reducer.lhs
index f71d1f62a270dfd15bdf702ae43175bbddc5e120..cc6d89fb62cc924c201edc33ef78114cfe1ed4e8 100644 (file)
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -3,14 +3,26 @@
 \frametitle{More than just toys}
 \pause
 \begin{itemize}
-  \item We designed a matrix reduction circuit\pause
+  \item We designed a reduction circuit in \clash{}\pause
   \item Simulation results in Haskell match VHDL simulation results\pause
   \item Synthesis completes without errors or warnings\pause
-  \item It runs at half the speed of a hand-coded VHDL design
+  \item For the same Virtex-4 FPGA: \pause
+    \begin{itemize}
+      \item Hand coded VHDL design runs at 200 MHz\pause
+      \item \clash{} design runs at around 85* MHz
+    \end{itemize}
 \end{itemize}
+\vspace{6em}
+\uncover<7->{\scriptsize{*Guestimate: design synthesized at 105 MHz, but with an Integer datapath instead of a floating point datapath.}}
 }\note[itemize]{
 \item Toys like the poly cpu one are good to give a quick demo
 \item But we used \clash{} to design 'real' hardware
 \item Reduction circuit sums the numbers in a row of a (sparse) matrix
-\item Half speed is nice, considering we don't optimize for speed
-}
\ No newline at end of file
+\item Nice speed considering we don't optimize for it
+}
+
+\begin{frame}[plain] 
+   \begin{centering} 
+      \includegraphics[height=\paperheight]{reducerschematic.png} 
+      \end{centering} 
+\end{frame} 
\ No newline at end of file