Merge branch 'haskel09talk' of http://git.stderr.nl/matthijs/projects/master-project

[matthijs/master-project/haskell-symposium-talk.git] / reducer.lhs

diff --git a/reducer.lhs b/reducer.lhs
index cc6d89fb62cc924c201edc33ef78114cfe1ed4e8..4d74c68ed188bc00b66f31730421be46ba86a204 100644 (file)
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -2,27 +2,22 @@
 \frame{
 \frametitle{More than just toys}
 \pause
+TODO: Plaatje van de reducer
 \begin{itemize}
-  \item We designed a reduction circuit in \clash{}\pause
+  \item We implemented a reduction circuit in \clash{}\pause
   \item Simulation results in Haskell match VHDL simulation results\pause
   \item Synthesis completes without errors or warnings\pause
-  \item For the same Virtex-4 FPGA: \pause
-    \begin{itemize}
-      \item Hand coded VHDL design runs at 200 MHz\pause
-      \item \clash{} design runs at around 85* MHz
-    \end{itemize}
+  \item Around half speed of handcoded and optimized VHDL \pause
 \end{itemize}
-\vspace{6em}
-\uncover<7->{\scriptsize{*Guestimate: design synthesized at 105 MHz, but with an Integer datapath instead of a floating point datapath.}}
 }\note[itemize]{
 \item Toys like the poly cpu one are good to give a quick demo
 \item But we used \clash{} to design 'real' hardware
 \item Reduction circuit sums the numbers in a row of a (sparse) matrix
-\item Nice speed considering we don't optimize for it
+\item Nice speed considering we don't optimize for it (only single example!)
 }
 
 \begin{frame}[plain] 
    \begin{centering} 
       \includegraphics[height=\paperheight]{reducerschematic.png} 
       \end{centering} 
-\end{frame} 
\ No newline at end of file
+\end{frame}