Hopefully finalized presentation

[matthijs/master-project/haskell-symposium-talk.git] / reducer.lhs

diff --git a/reducer.lhs b/reducer.lhs
index 03c688c520ac496f98c8657ca05968c9c96658d0..21baeeb9db140eb52b071981ba1403677a7b8313 100644 (file)
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -10,7 +10,7 @@
 \column{0.5\textwidth}
 \begin{itemize}
   \item We implemented a reduction circuit in \clash{}\pause
-  \item Simulation results in Haskell match VHDL simulation results\pause
+  \item Simulated first Haskell. VHDL simulation results match\pause
   \item Synthesis completes without errors or warnings\pause
   \item Around half speed of handcoded and optimized VHDL
 \end{itemize}
@@ -18,7 +18,9 @@
 }\note[itemize]{
 \item Toys like the poly cpu one are good to give a quick demo
 \item But we used \clash{} to design 'real' hardware
-\item Reduction circuit sums the numbers in a row of a (sparse) matrix
+\item Reduction circuit sums the numbers in a row, of different length
+\item It uses a pipelined adder: multiple rows in pipeline, rows longer than pipeline
+\item We hope you see this is not a trivial problem
 \item Nice speed considering we don't optimize for it (only single example!)
 }