Actually add the SVG of the compiler pipeline

[matthijs/master-project/dsd-paper.git] / cλash.lhs

diff --git a/cλash.lhs b/cλash.lhs
index c4a281f53f9d3e481545c29f745b401d9c30428e..b43aca82384bfb88c678106dc94b2f1ca7ee3bef 100644 (file)
--- a/cλash.lhs
+++ b/cλash.lhs
@@ -810,8 +810,8 @@ by an (optimizing) \VHDL\ synthesis tool.
         % value.
       \item[\bf{Multiple constructors with fields}]
         Algebraic datatypes with multiple constructors, where at least
-        one of these constructors has one or more fields are not
-        currently supported.
+        one of these constructors has one or more fields are currently not 
+        supported.
     \end{xlist}
 
   \subsection{Polymorphism}
@@ -1013,7 +1013,32 @@ by an (optimizing) \VHDL\ synthesis tool.
     
 \section{\CLaSH\ prototype}
 
-foo\par bar
+The \CLaSH\ language as presented above can be translated to \VHDL\ using
+the prototype \CLaSH\ compiler. This compiler allows experimentation with
+the \CLaSH\ language and allows for running \CLaSH\ designs on actual FPGA
+hardware.
+
+\begin{figure}
+\centerline{\includegraphics{compilerpipeline.svg}}
+\caption{\CLaSH\ compiler pipeline}
+\label{img:compilerpipeline}
+\end{figure}
+
+The prototype heavily uses \GHC, the Glasgow Haskell Compiler. 
+\Cref{img:compilerpipeline} shows the \CLaSH\ compiler pipeline. As you can 
+see, the front-end is completely reused from \GHC, which allows the \CLaSH\ 
+prototype to support most of the Haskell Language. The \GHC\ front-end 
+produces the program in the \emph{Core} format, which is a very small, 
+functional, typed language which is relatively easy to process.
+
+The second step in the compilation process is \emph{normalization}. This
+step runs a number of \emph{meaning preserving} transformations on the
+Core program, to bring it into a \emph{normal form}. This normal form
+has a number of restrictions that make the program similar to hardware.
+In particular, a program in normal form no longer has any polymorphism
+or higher order functions.
+
+The final step is a simple translation to \VHDL.
 
 \section{Use cases}
 As an example of a common hardware design where the use of higher-order
@@ -1126,7 +1151,7 @@ synchronous and untimed models of computation. Using so-called domain
 interfaces a designer can simulate electronic systems which have both analog 
 as digital parts. ForSyDe has several simulation and  synthesis backends, 
 though synthesis is restricted to the synchronous subset of the ForSyDe 
-language. Unlike \CLaSH\ there is no support for the automated synthesis of description that contain polymorphism or higher-order functions.
+language. Unlike \CLaSH\ there is no support for the automated synthesis of descriptions that contain polymorphism or higher-order functions.
 
 Lava~\cite{Lava} is a hardware description language that focuses on the 
 structural representation of hardware. Besides support for simulation and