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descriptions started in the early 1980s \cite{Cardelli1981, muFP,DAISY,FHDL},
a time which also saw the birth of the currently popular hardware description
languages such as \VHDL. The merit of using a functional language to describe
-hardware comes from the fact that basic combinatorial circuits are equivalent
-to mathematical functions and that functional languages are very good at
-describing and composing mathematical functions.
+hardware comes from the fact that combinatorial circuits can be directly
+modeled as mathematical functions and that functional languages are very good
+at describing and composing mathematical functions.
In an attempt to decrease the amount of work involved with creating all the
required tooling, such as parsers and type-checkers, many functional hardware
available in the functional hardware description languages that are embedded
in Haskell as a domain specific languages. As far as the authors know, such
extensive support for choice-elements is new in the domain of functional
-hardware description language. As the hardware descriptions are plain Haskell
-functions, these descriptions can be compiled for simulation using using the
-optimizing Haskell compiler \GHC.
+hardware description languages. As the hardware descriptions are plain Haskell
+functions, these descriptions can be compiled for simulation using an
+optimizing Haskell compiler such as the Glasgow Haskell Compiler (\GHC).
Where descriptions in a conventional hardware description language have an
explicit clock for the purpose state and synchronicity, the clock is implied
-in this research. The functions describe the behavior of the hardware between
+in this research. A developer describes the behavior of the hardware between
clock cycles, as such, only synchronous systems can be described. Many
-functional hardware description models signals as a stream of all values over
+functional hardware description model signals as a stream of all values over
time; state is then modeled as a delay on this stream of values. The approach
taken in this research is to make the current state of a circuit part of the
input of the function and the updated state part of the output.
netlist. This research also features a prototype translator called \CLaSH\
(pronounced: clash), which converts the Haskell code to equivalently behaving
synthesizable \VHDL\ code, ready to be converted to an actual netlist format
-by an optimizing \VHDL\ synthesis tool.
+by any (optimizing) \VHDL\ synthesis tool.
\section{Hardware description in Haskell}
\subsection{Function application}
The basic syntactic elements of a functional program are functions
and function application. These have a single obvious translation to a
- netlist: every function becomes a component, every function argument is an
- input port and the result value is of a function is an output port. This
- output port can have a complex type (such as a tuple), so having just a
- single output port does not create a limitation. Each function application
- in turn becomes a component instantiation. Here, the result of each
- argument expression is assigned to a signal, which is mapped to the
- corresponding input port. The output port of the function is also mapped
- to a signal, which is used as the result of the application itself.
+ netlist format:
+ \begin{inparaenum}
+ \item every function is translated to a component,
+ \item every function argument is translated to an input port,
+ \item the result value of a function is translated to an output port,
+ and
+ \item function applications are translated to component instantiations.
+ \end{inparaenum}
+ The output port can have a complex type (such as a tuple), so having just
+ a single output port does not pose any limitation. The arguments of a
+ function applications are assigned to a signal, which are then mapped to
+ the corresponding input ports of the component. The output port of the
+ function is also mapped to a signal, which is used as the result of the
+ application itself.
Since every top level function generates its own component, the
- hierarchy of function calls is reflected in the final netlist aswell,
+ hierarchy of function calls is reflected in the final netlist,% aswell,
creating a hierarchical description of the hardware. This separation in
different components makes the resulting \VHDL\ output easier to read and
debug.
In Haskell, choice can be achieved by a large set of language constructs,
consisting of: \hs{case} constructs, \hs{if-then-else} constructs,
pattern matching, and guards. The easiest of these are the \hs{case}
- constructs (and \hs{if} expressions, which can be very directly translated
- to \hs{case} expressions). A \hs{case} expression can in turn simply be
- translated to a conditional assignment in \VHDL, where the conditions use
- equality comparisons against the constructors in the \hs{case}
- expressions. We can see two versions of a contrived example, the first
+ constructs (\hs{if} expressions can be very directly translated to
+ \hs{case} expressions). % Choice elements are translated to multiplexers
+ % A \hs{case} expression can in turn simply be translated to a conditional
+ % assignment in \VHDL, where the conditions use equality comparisons
+ % against the constructors in the \hs{case} expressions.
+ We can see two versions of a contrived example, the first
using a \hs{case} construct and the other using a \hs{if-then-else}
constructs, in the code below. The example sums two values when they are
equal or non-equal (depending on the predicate given) and returns 0
completely new type, for which we provide the \VHDL\ translation
below. Type synonyms and renamings only define new names for
existing types, where synonyms are completely interchangeable and
- renamings need explicit conversion. Therefore, these do not need
+ renamings need explicit conversiona. Therefore, these do not need
any particular \VHDL\ translation, a synonym or renamed type will
just use the same representation as the original type. The
distinction between a renaming and a synonym does no longer matter
Haskell's builtin tuple types are also defined as single
constructor algebraic types and are translated according to this
- rule by the \CLaSH\ compiler. These types are translated to \VHDL\
- record types, with one field for every field in the constructor.
+ rule by the \CLaSH\ compiler.
+ % These types are translated to \VHDL\ record types, with one field
+ % for every field in the constructor.
\item[\bf{No fields}]
Algebraic datatypes with multiple constructors, but without any
fields are essentially a way to get an enumeration-like type
containing alternatives. Note that Haskell's \hs{Bool} type is also
defined as an enumeration type, but we have a fixed translation for
- that. These types are translated to \VHDL\ enumerations, with one
- value for each constructor. This allows references to these
- constructors to be translated to the corresponding enumeration value.
+ that.
+ % These types are translated to \VHDL\ enumerations, with one
+ % value for each constructor. This allows references to these
+ % constructors to be translated to the corresponding enumeration
+ % value.
\item[\bf{Multiple constructors with fields}]
Algebraic datatypes with multiple constructors, where at least
one of these constructors has one or more fields are not
valid option, as the language would then lose many of it mathematical
properties. In an effort to include the concept of state in pure
functions, the current value of the state is made an argument of the
- function; the updated state becomes part of the result.
+ function; the updated state becomes part of the result. A simple example
+ is adding an accumulator register to the earlier multiply-accumulate
+ circuit, of which the resulting netlist can be seen in
+ \Cref{img:mac-state}:
- A simple example is the description of an accumulator circuit:
\begin{code}
- acc :: Word -> State Word -> (State Word, Word)
- acc inp (State s) = (State s', outp)
+ macS a b (State c) = (State c', outp)
where
- outp = s + inp
- s' = outp
+ outp = mac a b c
+ c' = outp
\end{code}
- This approach makes the state of a function very explicit: which variables
+
+ \begin{figure}
+ \centerline{\includegraphics{mac-state}}
+ \caption{Stateful Multiply-Accumulate}
+ \label{img:mac-state}
+ \end{figure}
+
+ This approach makes the state of a circuit very explicit: which variables
are part of the state is completely determined by the type signature. This
approach to state is well suited to be used in combination with the
existing code and language features, such as all the choice constructs, as
projects / matthijs / master-project / dsd-paper.git / blobdiff