make paper version of highordcpu resemble compilable version of highordcpu

[matthijs/master-project/dsd-paper.git] / cλash.lhs

diff --git a/cλash.lhs b/cλash.lhs
index 3bcf41e75f41e3a0d507925cf1b78ea005e7b251..2fa6b8615ff78ce701ecefb496b9223b1bd57bbb 100644 (file)
--- a/cλash.lhs
+++ b/cλash.lhs
@@ -762,7 +762,7 @@ circuit~\cite{reductioncircuit} for floating point numbers.
         the rest of paper is: \hs{[a|n]}. Where the \hs{a} is the element 
         type, and \hs{n} is the length of the vector. Note that this is
         a notation used in this paper only, vectors are slightly more
-        elaborate in real \CLaSH\ programs.
+        verbose in real \CLaSH\ descriptions.
         % The state type of an 8 element register bank would then for example 
         % be:
 
@@ -1192,12 +1192,11 @@ the vectors of the \acro{FIR} code to a length of 4, is depicted in
 \subsection{Higher order CPU}
 
 \begin{code}
-fu op inputs (addr1, addr2) (State out) =
-  (State out', out)
+fu op inputs (addr1, addr2) regOut = (regIn, regOut)
   where
-    in1  = inputs!addr1
-    in2  = inputs!addr2
-    out' = op in1 in2
+    in1     = inputs!addr1
+    in2     = inputs!addr2
+    regIn   = op in1 in2
 \end{code}
 
 \begin{code}