Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project

* 'cλash' of http://git.stderr.nl/matthijs/projects/master-project:
  Unify all BuiltinBuilder functions.
  Give HighOrdAlu an and operation.
  Let tfvec_len and tfvec_elem give a proper error message.
  No longer use a view pattern in HsTools.

Conflicts:
	Generate.hs

diff --cc Generate.hs
index 17c3d494e6f74aae3dbc8b491fa98a37287eec65,7de216129dfbed6cf4d55fb4e415d00fbc746c19..7b8dcf0894fb0ca41296f08addd659d07868b651
--- 1/Generate.hs
--- 2/Generate.hs
+++ b/Generate.hs
@@@ -104,26 -150,20 +148,26 @@@ genFoldl' resVal f [folded_f, startVal
    let  len         = (tfvec_len . Var.varType) inVec
    let  genlabel       = mkVHDLExtId ("foldlVector" ++ (varToString inVec))
    let  blockLabel  = mkVHDLExtId ("foldlVector" ++ (varToString startVal))
 -  let  nPar        = AST.unsafeVHDLBasicId "n"
    let  range       = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
 -  let  genScheme   = AST.ForGn nPar range
 +  let  genScheme   = AST.ForGn (AST.unsafeVHDLBasicId "n") range
    -- Make the intermediate vector
    let  tmpVec      = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing
 -    -- Return the generate functions
 -  let genSm       = AST.GenerateSm genlabel genScheme []  [ AST.CSGSm (genFirstCell entity [startVal, inVec, resVal])
 -                                                          , AST.CSGSm (genOtherCell entity [startVal, inVec, resVal])
 -                                                          , AST.CSGSm (genLastCell entity [startVal, inVec, resVal])
 -                                                          ]
 -  return [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]]
 +  -- Get the entity name and port names
 +  let entity_id   = ent_id entity
 +  let argports    = map (Monad.liftM fst) (ent_args entity)
 +  let resport     = (Monad.liftM fst) (ent_res entity)
-     -- Return the generate functions
++  -- Return the generate functions
 +  let genSm       = AST.GenerateSm genlabel genScheme [] 
 +                      [ AST.CSGSm (genFirstCell (entity_id, argports, resport) 
 +                                    [startVal, inVec, resVal])
 +                      , AST.CSGSm (genOtherCell (entity_id, argports, resport) 
 +                                    [startVal, inVec, resVal])
 +                      , AST.CSGSm (genLastCell (entity_id, argports, resport) 
 +                                    [startVal, inVec, resVal])
 +                      ]
-   return $ AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]
++  return $ [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]]
    where
 -    genFirstCell :: Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm 
 -    genFirstCell entity [startVal, inVec, resVal] = cellGn
 +    genFirstCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
        where
          cellLabel    = mkVHDLExtId "firstcell"
          cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar)  AST.:=: (AST.PrimLit "0"))

diff --cc VHDL.hs
Simple merge