Merge branch 'master' of git://github.com/christiaanb/clash into cλash

* 'master' of git://github.com/christiaanb/clash:
  TFP has updated/remade. Change hardwaretypes accordingly
  Connect resetn port to states.
  Fix the resetn signal in the testbench, it is now correctly '0' for 3 ns, and after that '1'

diff --git a/cλash/CLasH/HardwareTypes.hs b/cλash/CLasH/HardwareTypes.hs
index c3eaf4396ef0eb2c65c991cfabdeef9eacd2a986..cff5c88568dd535d9b86b4059ed3166218c314b7 100644 (file)
--- a/cλash/CLasH/HardwareTypes.hs
+++ b/cλash/CLasH/HardwareTypes.hs
@@ -10,6 +10,8 @@ module CLasH.HardwareTypes
   , Bit(..)
   , State(..)
   , Vector
+  , resizeInt
+  , resizeWord
   , hwand
   , hwor
   , hwxor
@@ -27,8 +29,10 @@ import Types
 import qualified Data.Param.TFVec as TFVec
 import Data.Param.TFVec hiding (TFVec)
 import Data.RangedWord
-import Data.SizedInt
-import Data.SizedWord 
+import qualified Data.SizedInt as SizedInt
+import Data.SizedInt hiding (resize)
+import qualified Data.SizedWord as SizedWord
+import Data.SizedWord hiding (resize) 
 
 import Language.Haskell.TH.Lift
 import Data.Typeable
@@ -37,6 +41,12 @@ newtype State s = State s deriving (P.Show)
 
 type Vector = TFVec.TFVec
 
+resizeInt :: (NaturalT nT, NaturalT nT') => SizedInt nT -> SizedInt nT'
+resizeInt = SizedInt.resize
+
+resizeWord :: (NaturalT nT, NaturalT nT') => SizedWord nT -> SizedWord nT'
+resizeWord = SizedWord.resize
+
 -- The plain Bit type
 data Bit = High | Low
   deriving (P.Show, P.Eq, P.Read, Typeable)

diff --git a/cλash/CLasH/VHDL/Generate.hs b/cλash/CLasH/VHDL/Generate.hs
index d1bf3751e3209dc0d1b8b8f8453bdb225ba12b57..58810072de2dbcb322f9dca4073b9c8614b3a4d5 100644 (file)
--- a/cλash/CLasH/VHDL/Generate.hs
+++ b/cλash/CLasH/VHDL/Generate.hs
@@ -167,16 +167,18 @@ mkStateProcSm ::
 mkStateProcSm (old, new) = do
   nonempty <- hasNonEmptyType old 
   if nonempty 
-    then return [AST.CSPSm $ AST.ProcSm label [clk] [statement]]
+    then return [AST.CSPSm $ AST.ProcSm label [clockId,resetId] [statement]]
     else return []
   where
     label       = mkVHDLBasicId $ "state"
-    clk         = mkVHDLBasicId "clock"
     rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
     wform       = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing]
-    assign      = AST.SigAssign (varToVHDLName old) wform
-    rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
-    statement   = AST.IfSm rising_edge_clk [assign] [] Nothing
+    clk_assign      = AST.SigAssign (varToVHDLName old) wform
+    rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clockId)]
+    resetn_is_low  = (AST.PrimName $ AST.NSimple resetId) AST.:=: (AST.PrimLit "'0'")
+    reset_statement = []
+    clk_statement = [AST.ElseIf rising_edge_clk [clk_assign]]
+    statement   = AST.IfSm resetn_is_low reset_statement clk_statement Nothing
 
 
 -- | Transforms a core binding into a VHDL concurrent statement

diff --git a/cλash/CLasH/VHDL/Testbench.hs b/cλash/CLasH/VHDL/Testbench.hs
index bc23262c09b05c31efacd6f4a41f41235dadedea..2b31925c655e7bcf731a058948b66cd88f22ffc1 100644 (file)
--- a/cλash/CLasH/VHDL/Testbench.hs
+++ b/cλash/CLasH/VHDL/Testbench.hs
@@ -87,7 +87,7 @@ createTestbenchArch mCycles stimuli top testent= do
   (stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds)
   let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==:
                       AST.ConWforms []
-                                    (AST.Wform [AST.WformElem (AST.PrimLit "'1'") (Just $ AST.PrimLit "3 ns")])
+                                    (AST.Wform [AST.WformElem (AST.PrimLit "'0'") (Just $ AST.PrimLit "0 ns"), AST.WformElem (AST.PrimLit "'1'") (Just $ AST.PrimLit "3 ns")])
                                     Nothing)) : stimuliAssigns
   let clkProc     = createClkProc
   let arch = AST.ArchBody