Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project

* 'cλash' of http://git.stderr.nl/matthijs/projects/master-project:
  Generate proper VHDL for top level bindings with no arguments.
  Use is_local_var for limiting appsimpl and letsimpl.
  Add newline at the end of file.
  Add is_local_var predicate.
  Santize comment dashes position.
  Normalize all used global binders.

diff --combined CoreTools.hs
index 988825509cd33be0b85f4c58d058ce1ba8edf9dc,bd6f329c537ea93842bf5b221998cf47fb69085c..3bfe1a156dfc89826e6070d7255a854ad514add6
--- 1/CoreTools.hs
--- 2/CoreTools.hs
+++ b/CoreTools.hs
@@@ -38,10 -38,9 +38,10 @@@ import Prett
  
  -- | Evaluate a core Type representing type level int from the tfp
  -- library to a real int.
 -eval_tfp_int :: Type.Type -> Int
 -eval_tfp_int ty =
 +eval_tfp_int :: HscTypes.HscEnv -> Type.Type -> Int
 +eval_tfp_int env ty =
    unsafeRunGhc $ do
 +    GHC.setSession env
      -- Automatically import modules for any fully qualified identifiers
      setDynFlag DynFlags.Opt_ImplicitImportQualified
  
@@@ -223,4 -222,4 +223,4 @@@ getLiterals :: CoreSyn.CoreExpr -> [Cor
  getLiterals app@(CoreSyn.App _ _) = literals
    where
      (CoreSyn.Var f, args) = CoreSyn.collectArgs app
-     literals = filter (is_lit) args
+     literals = filter (is_lit) args