State newtype has been moved to CLasH.HardwareTypes

diff --git a/Alu.hs b/Alu.hs
index b7fff900642ca72ae2ec6f70958a4a656591bb51..1c60c0414886cbb975d18fb994a286beb46e1c24 100644 (file)
--- a/Alu.hs
+++ b/Alu.hs
@@ -12,8 +12,6 @@ mainIO = Sim.simulateIO exec initial_state
 
 dontcare = Low
 
-newtype State s = State s deriving (P.Show)
-
 program = [
             -- (addr, we, op)
             (High, Low, High), -- z = r1 and t (0) ; t = r1 (1)

diff --git a/cλash/CLasH/HardwareTypes.hs b/cλash/CLasH/HardwareTypes.hs
index 9209086db466642dde74e6d4967f418b1ea5a3e9..682cd05c46fbd2a1718216b3847d30e9b42360f2 100644 (file)
--- a/cλash/CLasH/HardwareTypes.hs
+++ b/cλash/CLasH/HardwareTypes.hs
@@ -8,6 +8,7 @@ module CLasH.HardwareTypes
   , module Data.SizedWord
   , module Prelude
   , Bit(..)
+  , State(..)
   , Vector
   , hwand
   , hwor
@@ -29,6 +30,8 @@ import Data.SizedWord
 import Language.Haskell.TH.Lift
 import Data.Typeable
 
+newtype State s = State s deriving (P.Show)
+
 type Vector = TFVec.TFVec
 
 -- The plain Bit type