Don't generate VHDL for substate extractor cases.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 6 Aug 2009 15:40:25 +0000 (17:40 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 6 Aug 2009 15:40:25 +0000 (17:40 +0200)
commitf0c06cad4df4d07d2d8542e6454cffb06f620719
tree0348dd3660996240aab7972eb9d5899d0f5e24d2
parent1208e784cccf1d2d6d290ec1609a64584e8ed555
Don't generate VHDL for substate extractor cases.
cλash/CLasH/VHDL/Generate.hs