From f0c06cad4df4d07d2d8542e6454cffb06f620719 Mon Sep 17 00:00:00 2001 From: Matthijs Kooijman Date: Thu, 6 Aug 2009 17:40:25 +0200 Subject: [PATCH] Don't generate VHDL for substate extractor cases. --- "c\316\273ash/CLasH/VHDL/Generate.hs" | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git "a/c\316\273ash/CLasH/VHDL/Generate.hs" "b/c\316\273ash/CLasH/VHDL/Generate.hs" index 431f379..5698ef8 100644 --- "a/c\316\273ash/CLasH/VHDL/Generate.hs" +++ "b/c\316\273ash/CLasH/VHDL/Generate.hs" @@ -160,7 +160,10 @@ mkConcSm (bndr, app@(CoreSyn.App _ _))= do -- A single alt case must be a selector. This means thee scrutinee is a simple -- variable, the alternative is a dataalt with a single non-wild binder that -- is also returned. -mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt])) = +mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt])) + -- Don't generate VHDL for substate extraction + | hasStateType bndr = return ([], []) + | otherwise = case alt of (CoreSyn.DataAlt dc, bndrs, (CoreSyn.Var sel_bndr)) -> do case List.elemIndex sel_bndr bndrs of -- 2.30.2