Don't generate input ports for State arguments.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 6 Aug 2009 14:21:32 +0000 (16:21 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 6 Aug 2009 14:21:32 +0000 (16:21 +0200)
commitedb200f40c64361b24ecc8af187f724bd5d6d9bb
tree22c7e96ce7e447322a3bbddcdc4c1b7655c6e1de
parentfda239f0ae8fc6a2250e6719c3f564c9b2390c4a
Don't generate input ports for State arguments.
cλash/CLasH/VHDL/Generate.hs