Don't generate VHDL for state packing.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 6 Aug 2009 14:20:51 +0000 (16:20 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 6 Aug 2009 14:20:51 +0000 (16:20 +0200)
commitfda239f0ae8fc6a2250e6719c3f564c9b2390c4a
tree8aadbcb33c179a85f7168ced680a3331a0b9dfc1
parent492679b60261a7e041adb2480ea9799b0db0bfa2
Don't generate VHDL for state packing.
cλash/CLasH/VHDL/Generate.hs