Fix the resetn signal in the testbench, it is now correctly '0' for 3 ns, and after...
authorChristiaan Baaij <christiaan.baaij@gmail.com>
Thu, 20 Aug 2009 11:56:10 +0000 (13:56 +0200)
committerChristiaan Baaij <christiaan.baaij@gmail.com>
Thu, 20 Aug 2009 11:56:10 +0000 (13:56 +0200)
commitbfe8487df7ef91568b94e6646bb2f474469fb8c2
tree76d5d368996b028b01a27a494eec68d2e83aaa1b
parenta09063e81d573bfa513d30ae97dba95485dc67e9
Fix the resetn signal in the testbench, it is now correctly '0' for 3 ns, and after that '1'
cλash/CLasH/VHDL/Testbench.hs