Allow explicit empty VHDL types using Maybe.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 6 Aug 2009 15:08:25 +0000 (17:08 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Thu, 6 Aug 2009 15:12:08 +0000 (17:12 +0200)
commitad9bc80c39c42f645c76c65e1d3833148b854c1e
treebced4841509c4672b9c57bfd3dfbcaacd5b83cbb
parentedb200f40c64361b24ecc8af187f724bd5d6d9bb
Allow explicit empty VHDL types using Maybe.

The VHDL type generating functions can now return "Nothing" to mean that an
empty type would be generated. There are still some spots (builtin
functions mostly) that should handle this more gracefully, but it works
for now. Only single-constructor zero-argument algebraic types generate
the empty type currently, e.g. ().
cλash/CLasH/Translator/TranslatorTypes.hs
cλash/CLasH/VHDL/Generate.hs
cλash/CLasH/VHDL/VHDLTools.hs