Make register_bank work, with a bunch of changes.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index 57bebfc12ab0265369ecb7028a6a8740c579d2d6..b85d6ff0be288e7db0ec57ca886fae79cbc6ec09 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -205,6 +205,10 @@ mkConcSm sigs (UncondDef src dst) = do
       case expr of
         (EqLit id lit) ->
           (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
+        (Literal lit) ->
+          AST.PrimLit lit
+        (Eq a b) ->
+          (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
 
 mkConcSm sigs (CondDef cond true false dst) = do
   let cond_expr  = mkIdExpr sigs cond