Make register_bank work, with a bunch of changes.

[matthijs/master-project/cλash.git] / FlattenTypes.hs

diff --git a/FlattenTypes.hs b/FlattenTypes.hs
index c7e0c1e79e6eca5c771c455052b2860b467ca870..092baff4911fdcb6789399ec613c09293fe30f02 100644 (file)
--- a/FlattenTypes.hs
+++ b/FlattenTypes.hs
@@ -99,6 +99,8 @@ data SigDef =
 -- | An expression on signals
 data SignalExpr = 
   EqLit SignalId String -- ^ Is the given signal equal to the given (VHDL) literal
+  | Literal String -- ^ A literal value
+  | Eq SignalId SignalId -- ^ A comparison between to signals
   deriving (Show, Eq)
 
 -- Returns the function used by the given SigDef, if any