2 -- Some types used by the VHDL module.
4 {-# LANGUAGE TemplateHaskell #-}
8 import qualified Control.Monad.Trans.State as State
9 import qualified Data.Map as Map
11 import qualified Data.Accessor.Template
17 import qualified ForSyDe.Backend.VHDL.AST as AST
23 type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
24 -- | A mapping from a haskell structure to the corresponding VHDL port
25 -- signature, or Nothing for values that do not translate to a port.
26 type VHDLSignalMap = HsValueMap VHDLSignalMapElement
28 -- A description of a VHDL entity. Contains both the entity itself as well as
29 -- info on how to map a haskell value (argument / result) on to the entity's
31 data Entity = Entity {
32 ent_id :: AST.VHDLId, -- The id of the entity
33 ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
34 ent_res :: VHDLSignalMap -- A mapping of the function result to port names
37 -- A orderable equivalent of CoreSyn's Type for use as a map key
38 newtype OrdType = OrdType { getType :: Type.Type }
39 instance Eq OrdType where
40 (OrdType a) == (OrdType b) = Type.tcEqType a b
41 instance Ord OrdType where
42 compare (OrdType a) (OrdType b) = Type.tcCmpType a b
44 -- A map of a Core type to the corresponding type name
45 type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
47 -- A map of a vector Core type to the coressponding VHDL functions
48 type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
50 -- A map of a Haskell function to a hardware signature
51 type SignatureMap = Map.Map HsFunction Entity
53 -- A map of a builtin function to VHDL function builder
54 type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
56 data VHDLSession = VHDLSession {
57 -- | A map of Core type -> VHDL Type
59 -- | A map of vector Core type -> VHDL type function
60 vsTypeFuns_ :: TypeFunMap,
61 -- | A map of HsFunction -> hardware signature (entity name, port names,
63 vsSignatures_ :: SignatureMap,
64 -- | A map of Vector HsFunctions -> VHDL function call
65 vsNameTable_ :: NameTable
69 $( Data.Accessor.Template.deriveAccessors ''VHDLSession )
71 -- | The state containing a VHDL Session
72 type VHDLState = State.State VHDLSession
74 -- | A substate containing just the types
75 type TypeState = State.State TypeMap
77 -- vim: set ts=8 sw=2 sts=2 expandtab: