2 -- Some types used by the VHDL module.
4 {-# LANGUAGE TemplateHaskell #-}
8 import qualified Control.Monad.Trans.State as State
9 import qualified Data.Map as Map
11 import qualified Data.Accessor.Template
15 import qualified CoreSyn
18 import qualified ForSyDe.Backend.VHDL.AST as AST
22 -- A description of a port of an entity
23 type Port = (AST.VHDLId, AST.TypeMark)
25 -- A description of a VHDL entity. Contains both the entity itself as well as
26 -- info on how to map a haskell value (argument / result) on to the entity's
28 data Entity = Entity {
29 ent_id :: AST.VHDLId, -- The id of the entity
30 ent_args :: [Port], -- A mapping of each function argument to port names
31 ent_res :: Port -- A mapping of the function result to port names
34 -- A orderable equivalent of CoreSyn's Type for use as a map key
35 newtype OrdType = OrdType { getType :: Type.Type }
36 instance Eq OrdType where
37 (OrdType a) == (OrdType b) = Type.tcEqType a b
38 instance Ord OrdType where
39 compare (OrdType a) (OrdType b) = Type.tcCmpType a b
41 data HType = StdType OrdType |
42 ADTType String [HType] |
50 -- A map of a Core type to the corresponding type name
51 type TypeMap = Map.Map HType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
53 -- A map of a vector Core element type and function name to the coressponding
54 -- VHDLId of the function and the function body.
55 type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
57 -- A map of a Haskell function to a hardware signature
58 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
60 type TfpIntMap = Map.Map OrdType Int
62 data TypeState = TypeState {
63 -- | A map of Core type -> VHDL Type
65 -- | A list of type declarations
66 vsTypeDecls_ :: [AST.PackageDecItem],
67 -- | A map of vector Core type -> VHDL type function
68 vsTypeFuns_ :: TypeFunMap,
69 vsTfpInts_ :: TfpIntMap
72 $( Data.Accessor.Template.deriveAccessors ''TypeState )
73 -- Define an empty TypeState
74 emptyTypeState = TypeState Map.empty [] Map.empty Map.empty
76 type TypeSession = State.State TypeState
78 data VHDLState = VHDLState {
79 -- | A subtype with typing info
81 -- | A map of HsFunction -> hardware signature (entity name, port names,
83 vsSignatures_ :: SignatureMap
87 $( Data.Accessor.Template.deriveAccessors ''VHDLState )
89 -- | The state containing a VHDL Session
90 type VHDLSession = State.State VHDLState
92 -- A function that generates VHDL for a builtin function
94 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
95 -> CoreSyn.CoreBndr -- ^ The function called
96 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
97 -- dictionary arguments).
98 -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
100 -- A map of a builtin function to VHDL function builder
101 type NameTable = Map.Map String (Int, BuiltinBuilder )
103 -- vim: set ts=8 sw=2 sts=2 expandtab: