4 import qualified Control.Monad as Monad
5 import qualified Data.Map as Map
7 import qualified Data.Either as Either
9 import Data.Accessor.MonadState as MonadState
13 import qualified ForSyDe.Backend.VHDL.AST as AST
19 import qualified IdInfo
20 import qualified Literal
22 import qualified TyCon
31 -----------------------------------------------------------------------------
32 -- Functions to generate VHDL for builtin functions
33 -----------------------------------------------------------------------------
35 -- | A function to wrap a builder-like function that expects its arguments to
38 (dst -> func -> [AST.Expr] -> res)
39 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
40 genExprArgs wrap dst func args = wrap dst func args'
41 where args' = map (either (varToVHDLExpr.exprToVar) id) args
43 -- | A function to wrap a builder-like function that expects its arguments to
46 (dst -> func -> [Var.Var] -> res)
47 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
48 genVarArgs wrap dst func args = wrap dst func args'
50 args' = map exprToVar exprargs
51 -- Check (rather crudely) that all arguments are CoreExprs
52 (exprargs, []) = Either.partitionEithers args
54 -- | A function to wrap a builder-like function that expects its arguments to
57 (dst -> func -> [Literal.Literal] -> res)
58 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
59 genLitArgs wrap dst func args = wrap dst func args'
61 args' = map exprToLit litargs
62 -- FIXME: Check if we were passed an CoreSyn.App
63 litargs = concat (map getLiterals exprargs)
64 (exprargs, []) = Either.partitionEithers args
66 -- | A function to wrap a builder-like function that produces an expression
67 -- and expects it to be assigned to the destination.
69 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> VHDLSession AST.Expr)
70 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> VHDLSession [AST.ConcSm])
71 genExprRes wrap dst func args = do
72 expr <- wrap dst func args
73 return $ [mkUncondAssign dst expr]
75 -- | Generate a binary operator application. The first argument should be a
76 -- constructor from the AST.Expr type, e.g. AST.And.
77 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
78 genOperator2 op = genExprArgs $ genExprRes (genOperator2' op)
79 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
80 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
82 -- | Generate a unary operator application
83 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
84 genOperator1 op = genExprArgs $ genExprRes (genOperator1' op)
85 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
86 genOperator1' op _ f [arg] = return $ op arg
88 -- | Generate a function call from the destination binder, function name and a
89 -- list of expressions (its arguments)
90 genFCall :: Bool -> BuiltinBuilder
91 genFCall switch = genExprArgs $ genExprRes (genFCall' switch)
92 genFCall' :: Bool -> Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
93 genFCall' switch (Left res) f args = do
94 let fname = varToString f
95 let el_ty = if switch then (Var.varType res) else ((tfvec_elem . Var.varType) res)
96 id <- MonadState.lift vsType $ vectorFunId el_ty fname
97 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
98 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
99 genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
101 genFromSizedWord :: BuiltinBuilder
102 genFromSizedWord = genExprArgs $ genExprRes genFromSizedWord'
103 genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
104 genFromSizedWord' (Left res) f args = do
105 let fname = varToString f
106 return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $
107 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
108 genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
110 -- FIXME: I'm calling genLitArgs which is very specific function,
111 -- which needs to be fixed as well
112 genFromInteger :: BuiltinBuilder
113 genFromInteger = genLitArgs $ genExprRes genFromInteger'
114 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> VHDLSession AST.Expr
115 genFromInteger' (Left res) f lits =
116 return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
117 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
120 (tycon, args) = Type.splitTyConApp ty
121 name = Name.getOccString (TyCon.tyConName tycon)
123 "SizedInt" -> sized_int_len ty
124 "SizedWord" -> sized_word_len ty
126 "SizedInt" -> toSignedId
127 "SizedWord" -> toUnsignedId
129 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
132 -- | Generate a generate statement for the builtin function "map"
133 genMap :: BuiltinBuilder
134 genMap (Left res) f [Left mapped_f, Left (Var arg)] =
135 -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
136 -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
137 -- we must index it (which we couldn't if it was a VHDL Expr, since only
138 -- VHDLNames can be indexed).
140 -- Setup the generate scheme
141 len = (tfvec_len . Var.varType) res
142 -- TODO: Use something better than varToString
143 label = mkVHDLExtId ("mapVector" ++ (varToString res))
144 n_id = mkVHDLBasicId "n"
145 n_expr = idToVHDLExpr n_id
146 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
147 genScheme = AST.ForGn n_id range
149 -- Create the content of the generate statement: Applying the mapped_f to
150 -- each of the elements in arg, storing to each element in res
151 resname = mkIndexedName (varToVHDLName res) n_expr
152 argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
154 let (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
155 let valargs = get_val_args (Var.varType real_f) already_mapped_args
156 app_concsms <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
157 -- Return the generate statement
158 return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
160 genMap' (Right name) _ _ = error $ "\nGenerate.genMap': Cannot generate map function call assigned to a VHDLName: " ++ show name
162 genZipWith :: BuiltinBuilder
163 genZipWith = genVarArgs genZipWith'
164 genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
165 genZipWith' (Left res) f args@[zipped_f, arg1, arg2] =
167 -- Setup the generate scheme
168 len = (tfvec_len . Var.varType) res
169 -- TODO: Use something better than varToString
170 label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
171 n_id = mkVHDLBasicId "n"
172 n_expr = idToVHDLExpr n_id
173 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
174 genScheme = AST.ForGn n_id range
176 -- Create the content of the generate statement: Applying the zipped_f to
177 -- each of the elements in arg1 and arg2, storing to each element in res
178 resname = mkIndexedName (varToVHDLName res) n_expr
179 argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
180 argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
182 app_concsms <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2]
183 -- Return the generate functions
184 return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
186 genFoldl :: BuiltinBuilder
187 genFoldl = genFold True
189 genFoldr :: BuiltinBuilder
190 genFoldr = genFold False
192 genFold :: Bool -> BuiltinBuilder
193 genFold left = genVarArgs (genFold' left)
194 genFold' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
195 -- Special case for an empty input vector, just assign start to res
196 genFold' left (Left res) _ [_, start, vec] | len == 0 = return [mkUncondAssign (Left res) (varToVHDLExpr start)]
197 where len = (tfvec_len . Var.varType) vec
198 genFold' left (Left res) f [folded_f, start, vec] = do
199 -- evec is (TFVec n), so it still needs an element type
200 let (nvec, _) = splitAppTy (Var.varType vec)
201 -- Put the type of the start value in nvec, this will be the type of our
203 let tmp_ty = Type.mkAppTy nvec (Var.varType start)
204 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
205 tmp_vhdl_ty <- MonadState.lift vsType $ vhdl_ty error_msg tmp_ty
206 -- Setup the generate scheme
207 let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec))
208 let block_label = mkVHDLExtId ("foldlVector" ++ (varToString start))
209 let gen_range = if left then AST.ToRange (AST.PrimLit "0") len_min_expr
210 else AST.DownRange len_min_expr (AST.PrimLit "0")
211 let gen_scheme = AST.ForGn n_id gen_range
212 -- Make the intermediate vector
213 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
214 -- Create the generate statement
215 cells <- sequence [genFirstCell, genOtherCell]
216 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
217 -- Assign tmp[len-1] or tmp[0] to res
218 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (if left then
219 (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) else
220 (mkIndexedName tmp_name (AST.PrimLit "0")))
221 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
222 return [AST.CSBSm block]
225 len = (tfvec_len . Var.varType) vec
226 -- An id for the counter
227 n_id = mkVHDLBasicId "n"
228 n_cur = idToVHDLExpr n_id
229 -- An expression for previous n
230 n_prev = if left then (n_cur AST.:-: (AST.PrimLit "1"))
231 else (n_cur AST.:+: (AST.PrimLit "1"))
232 -- An expression for len-1
233 len_min_expr = (AST.PrimLit $ show (len-1))
234 -- An id for the tmp result vector
235 tmp_id = mkVHDLBasicId "tmp"
236 tmp_name = AST.NSimple tmp_id
237 -- Generate parts of the fold
238 genFirstCell, genOtherCell :: VHDLSession AST.GenerateSm
240 let cond_label = mkVHDLExtId "firstcell"
241 -- if n == 0 or n == len-1
242 let cond_scheme = AST.IfGn $ n_cur AST.:=: (if left then (AST.PrimLit "0")
243 else (AST.PrimLit $ show (len-1)))
244 -- Output to tmp[current n]
245 let resname = mkIndexedName tmp_name n_cur
247 let argexpr1 = varToVHDLExpr start
248 -- Input from vec[current n]
249 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
250 app_concsms <- genApplication (Right resname) folded_f ( if left then
251 [Right argexpr1, Right argexpr2]
253 [Right argexpr2, Right argexpr1]
255 -- Return the conditional generate part
256 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
259 let cond_label = mkVHDLExtId "othercell"
260 -- if n > 0 or n < len-1
261 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (if left then (AST.PrimLit "0")
262 else (AST.PrimLit $ show (len-1)))
263 -- Output to tmp[current n]
264 let resname = mkIndexedName tmp_name n_cur
265 -- Input from tmp[previous n]
266 let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
267 -- Input from vec[current n]
268 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
269 app_concsms <- genApplication (Right resname) folded_f ( if left then
270 [Right argexpr1, Right argexpr2]
272 [Right argexpr2, Right argexpr1]
274 -- Return the conditional generate part
275 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
277 -- | Generate a generate statement for the builtin function "zip"
278 genZip :: BuiltinBuilder
279 genZip = genVarArgs genZip'
280 genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
281 genZip' (Left res) f args@[arg1, arg2] =
283 -- Setup the generate scheme
284 len = (tfvec_len . Var.varType) res
285 -- TODO: Use something better than varToString
286 label = mkVHDLExtId ("zipVector" ++ (varToString res))
287 n_id = mkVHDLBasicId "n"
288 n_expr = idToVHDLExpr n_id
289 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
290 genScheme = AST.ForGn n_id range
291 resname' = mkIndexedName (varToVHDLName res) n_expr
292 argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
293 argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
295 labels <- MonadState.lift vsType $ getFieldLabels (tfvec_elem (Var.varType res))
296 let resnameA = mkSelectedName resname' (labels!!0)
297 let resnameB = mkSelectedName resname' (labels!!1)
298 let resA_assign = mkUncondAssign (Right resnameA) argexpr1
299 let resB_assign = mkUncondAssign (Right resnameB) argexpr2
300 -- Return the generate functions
301 return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
303 -- | Generate a generate statement for the builtin function "unzip"
304 genUnzip :: BuiltinBuilder
305 genUnzip = genVarArgs genUnzip'
306 genUnzip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
307 genUnzip' (Left res) f args@[arg] =
309 -- Setup the generate scheme
310 len = (tfvec_len . Var.varType) arg
311 -- TODO: Use something better than varToString
312 label = mkVHDLExtId ("unzipVector" ++ (varToString res))
313 n_id = mkVHDLBasicId "n"
314 n_expr = idToVHDLExpr n_id
315 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
316 genScheme = AST.ForGn n_id range
317 resname' = varToVHDLName res
318 argexpr' = mkIndexedName (varToVHDLName arg) n_expr
320 reslabels <- MonadState.lift vsType $ getFieldLabels (Var.varType res)
321 arglabels <- MonadState.lift vsType $ getFieldLabels (tfvec_elem (Var.varType arg))
322 let resnameA = mkIndexedName (mkSelectedName resname' (reslabels!!0)) n_expr
323 let resnameB = mkIndexedName (mkSelectedName resname' (reslabels!!1)) n_expr
324 let argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!0)
325 let argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!1)
326 let resA_assign = mkUncondAssign (Right resnameA) argexprA
327 let resB_assign = mkUncondAssign (Right resnameB) argexprB
328 -- Return the generate functions
329 return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
331 genCopy :: BuiltinBuilder
332 genCopy = genVarArgs genCopy'
333 genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
334 genCopy' (Left res) f args@[arg] =
336 resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others)
337 (AST.PrimName $ (varToVHDLName arg))]
338 out_assign = mkUncondAssign (Left res) resExpr
342 genConcat :: BuiltinBuilder
343 genConcat = genVarArgs genConcat'
344 genConcat' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
345 genConcat' (Left res) f args@[arg] =
347 -- Setup the generate scheme
348 len1 = (tfvec_len . Var.varType) arg
349 (_, nvec) = splitAppTy (Var.varType arg)
350 len2 = tfvec_len nvec
351 -- TODO: Use something better than varToString
352 label = mkVHDLExtId ("concatVector" ++ (varToString res))
353 n_id = mkVHDLBasicId "n"
354 n_expr = idToVHDLExpr n_id
355 fromRange = n_expr AST.:*: (AST.PrimLit $ show len2)
356 genScheme = AST.ForGn n_id range
357 -- Create the content of the generate statement: Applying the mapped_f to
358 -- each of the elements in arg, storing to each element in res
359 toRange = (n_expr AST.:*: (AST.PrimLit $ show len2)) AST.:+: (AST.PrimLit $ show (len2-1))
360 range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len1-1))
361 resname = vecSlice fromRange toRange
362 argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
363 out_assign = mkUncondAssign (Right resname) argexpr
365 -- Return the generate statement
366 return [AST.CSGSm $ AST.GenerateSm label genScheme [] [out_assign]]
368 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
369 (AST.ToRange init last))
371 genIteraten :: BuiltinBuilder
372 genIteraten dst f args = genIterate dst f (tail args)
374 genIterate :: BuiltinBuilder
375 genIterate = genIterateOrGenerate True
377 genGeneraten :: BuiltinBuilder
378 genGeneraten dst f args = genGenerate dst f (tail args)
380 genGenerate :: BuiltinBuilder
381 genGenerate = genIterateOrGenerate False
383 genIterateOrGenerate :: Bool -> BuiltinBuilder
384 genIterateOrGenerate iter = genVarArgs (genIterateOrGenerate' iter)
385 genIterateOrGenerate' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
386 -- Special case for an empty input vector, just assign start to res
387 genIterateOrGenerate' iter (Left res) _ [app_f, start] | len == 0 = return [mkUncondAssign (Left res) (AST.PrimLit "\"\"")]
388 where len = (tfvec_len . Var.varType) res
389 genIterateOrGenerate' iter (Left res) f [app_f, start] = do
390 -- -- evec is (TFVec n), so it still needs an element type
391 -- let (nvec, _) = splitAppTy (Var.varType vec)
392 -- -- Put the type of the start value in nvec, this will be the type of our
393 -- -- temporary vector
394 let tmp_ty = Var.varType res
395 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
396 tmp_vhdl_ty <- MonadState.lift vsType $ vhdl_ty error_msg tmp_ty
397 -- Setup the generate scheme
398 let gen_label = mkVHDLExtId ("iterateVector" ++ (varToString start))
399 let block_label = mkVHDLExtId ("iterateVector" ++ (varToString res))
400 let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr
401 let gen_scheme = AST.ForGn n_id gen_range
402 -- Make the intermediate vector
403 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
404 -- Create the generate statement
405 cells <- sequence [genFirstCell, genOtherCell]
406 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
407 -- Assign tmp[len-1] or tmp[0] to res
408 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr tmp_name
409 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
410 return [AST.CSBSm block]
413 len = (tfvec_len . Var.varType) res
414 -- An id for the counter
415 n_id = mkVHDLBasicId "n"
416 n_cur = idToVHDLExpr n_id
417 -- An expression for previous n
418 n_prev = n_cur AST.:-: (AST.PrimLit "1")
419 -- An expression for len-1
420 len_min_expr = (AST.PrimLit $ show (len-1))
421 -- An id for the tmp result vector
422 tmp_id = mkVHDLBasicId "tmp"
423 tmp_name = AST.NSimple tmp_id
424 -- Generate parts of the fold
425 genFirstCell, genOtherCell :: VHDLSession AST.GenerateSm
427 let cond_label = mkVHDLExtId "firstcell"
428 -- if n == 0 or n == len-1
429 let cond_scheme = AST.IfGn $ n_cur AST.:=: (AST.PrimLit "0")
430 -- Output to tmp[current n]
431 let resname = mkIndexedName tmp_name n_cur
433 let argexpr = varToVHDLExpr start
434 let startassign = mkUncondAssign (Right resname) argexpr
435 app_concsms <- genApplication (Right resname) app_f [Right argexpr]
436 -- Return the conditional generate part
437 return $ AST.GenerateSm cond_label cond_scheme [] (if iter then
444 let cond_label = mkVHDLExtId "othercell"
445 -- if n > 0 or n < len-1
446 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (AST.PrimLit "0")
447 -- Output to tmp[current n]
448 let resname = mkIndexedName tmp_name n_cur
449 -- Input from tmp[previous n]
450 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
451 app_concsms <- genApplication (Right resname) app_f [Right argexpr]
452 -- Return the conditional generate part
453 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
456 -----------------------------------------------------------------------------
457 -- Function to generate VHDL for applications
458 -----------------------------------------------------------------------------
460 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
461 -> CoreSyn.CoreBndr -- ^ The function to apply
462 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
463 -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements
464 genApplication dst f args =
465 case Var.globalIdVarDetails f of
466 IdInfo.DataConWorkId dc -> case dst of
467 -- It's a datacon. Create a record from its arguments.
469 -- We have the bndr, so we can get at the type
470 labels <- MonadState.lift vsType $ getFieldLabels (Var.varType bndr)
471 return $ zipWith mkassign labels $ map (either exprToVHDLExpr id) args
473 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
475 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
476 mkUncondAssign (Right sel_name) arg
477 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconstructor application without an original binder"
478 IdInfo.VanillaGlobal -> do
479 -- It's a global value imported from elsewhere. These can be builtin
480 -- functions. Look up the function name in the name table and execute
481 -- the associated builder if there is any and the argument count matches
482 -- (this should always be the case if it typechecks, but just to be
484 case (Map.lookup (varToString f) globalNameTable) of
485 Just (arg_count, builder) ->
486 if length args == arg_count then
489 error $ "\nGenerate.genApplication(VanillaGlobal): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
490 Nothing -> error $ "\nGenerate.genApplication(VanillaGlobal): Using function from another module that is not a known builtin: " ++ pprString f
491 IdInfo.NotGlobalId -> do
492 signatures <- getA vsSignatures
493 -- This is a local id, so it should be a function whose definition we
494 -- have and which can be turned into a component instantiation.
496 signature = Maybe.fromMaybe
497 (error $ "\nGenerate.genApplication: Using function '" ++ (varToString f) ++ "' without signature? This should not happen!")
498 (Map.lookup f signatures)
499 entity_id = ent_id signature
500 -- TODO: Using show here isn't really pretty, but we'll need some
501 -- unique-ish value...
502 label = "comp_ins_" ++ (either show prettyShow) dst
503 portmaps = mkAssocElems (map (either exprToVHDLExpr id) args) ((either varToVHDLName id) dst) signature
505 return [mkComponentInst label entity_id portmaps]
506 IdInfo.ClassOpId cls -> do
507 -- FIXME: Not looking for what instance this class op is called for
508 -- Is quite stupid of course.
509 case (Map.lookup (varToString f) globalNameTable) of
510 Just (arg_count, builder) ->
511 if length args == arg_count then
514 error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
515 Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f
516 details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
518 -----------------------------------------------------------------------------
519 -- Functions to generate functions dealing with vectors.
520 -----------------------------------------------------------------------------
522 -- Returns the VHDLId of the vector function with the given name for the given
523 -- element type. Generates -- this function if needed.
524 vectorFunId :: Type.Type -> String -> TypeSession AST.VHDLId
525 vectorFunId el_ty fname = do
526 let error_msg = "\nGenerate.vectorFunId: Can not construct vector function for element: " ++ pprString el_ty
527 elemTM <- vhdl_ty error_msg el_ty
528 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
529 -- the VHDLState or something.
530 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
531 typefuns <- getA vsTypeFuns
532 case Map.lookup (OrdType el_ty, fname) typefuns of
533 -- Function already generated, just return it
534 Just (id, _) -> return id
535 -- Function not generated yet, generate it
537 let functions = genUnconsVectorFuns elemTM vectorTM
538 case lookup fname functions of
540 modA vsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, (fst body))
541 mapM_ (vectorFunId el_ty) (snd body)
543 Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname
545 function_id = mkVHDLExtId fname
547 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
548 -> AST.TypeMark -- ^ type of the vector
549 -> [(String, (AST.SubProgBody, [String]))]
550 genUnconsVectorFuns elemTM vectorTM =
551 [ (exId, (AST.SubProgBody exSpec [] [exExpr],[]))
552 , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr,replaceRet],[]))
553 , (headId, (AST.SubProgBody headSpec [] [headExpr],[]))
554 , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[]))
555 , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[]))
556 , (tailId, (AST.SubProgBody tailSpec [AST.SPVD tailVar] [tailExpr, tailRet],[]))
557 , (takeId, (AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet],[]))
558 , (dropId, (AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet],[]))
559 , (plusgtId, (AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet],[]))
560 , (emptyId, (AST.SubProgBody emptySpec [AST.SPCD emptyVar] [emptyExpr],[]))
561 , (singletonId, (AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet],[]))
562 , (copynId, (AST.SubProgBody copynSpec [AST.SPVD copynVar] [copynExpr],[]))
563 , (selId, (AST.SubProgBody selSpec [AST.SPVD selVar] [selFor, selRet],[]))
564 , (ltplusId, (AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet],[]))
565 , (plusplusId, (AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet],[]))
566 , (lengthTId, (AST.SubProgBody lengthTSpec [] [lengthTExpr],[]))
567 , (shiftlId, (AST.SubProgBody shiftlSpec [AST.SPVD shiftlVar] [shiftlExpr, shiftlRet], [initId]))
568 , (shiftrId, (AST.SubProgBody shiftrSpec [AST.SPVD shiftrVar] [shiftrExpr, shiftrRet], [tailId]))
569 , (nullId, (AST.SubProgBody nullSpec [] [nullExpr], []))
570 , (rotlId, (AST.SubProgBody rotlSpec [AST.SPVD rotlVar] [rotlExpr, rotlRet], [nullId, lastId, initId]))
571 , (rotrId, (AST.SubProgBody rotrSpec [AST.SPVD rotrVar] [rotrExpr, rotrRet], [nullId, tailId, headId]))
572 , (reverseId, (AST.SubProgBody reverseSpec [AST.SPVD reverseVar] [reverseFor, reverseRet], []))
575 ixPar = AST.unsafeVHDLBasicId "ix"
576 vecPar = AST.unsafeVHDLBasicId "vec"
577 vec1Par = AST.unsafeVHDLBasicId "vec1"
578 vec2Par = AST.unsafeVHDLBasicId "vec2"
579 nPar = AST.unsafeVHDLBasicId "n"
580 iId = AST.unsafeVHDLBasicId "i"
582 aPar = AST.unsafeVHDLBasicId "a"
583 fPar = AST.unsafeVHDLBasicId "f"
584 sPar = AST.unsafeVHDLBasicId "s"
585 resId = AST.unsafeVHDLBasicId "res"
586 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
587 AST.IfaceVarDec ixPar naturalTM] elemTM
588 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
589 (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName $
591 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
592 , AST.IfaceVarDec iPar naturalTM
593 , AST.IfaceVarDec aPar elemTM
595 -- variable res : fsvec_x (0 to vec'length-1);
598 (AST.SubtypeIn vectorTM
599 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
600 [AST.ToRange (AST.PrimLit "0")
601 (AST.PrimName (AST.NAttribute $
602 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
603 (AST.PrimLit "1")) ]))
605 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
606 replaceExpr = AST.NSimple resId AST.:=
607 (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NSimple iPar) AST.:-: AST.PrimLit "1") AST.:&:
608 AST.PrimName (AST.NSimple aPar) AST.:&:
609 vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1")
610 ((AST.PrimName (AST.NAttribute $
611 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))
612 AST.:-: AST.PrimLit "1"))
613 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
614 vecSlice init last = AST.PrimName (AST.NSlice
617 (AST.ToRange init last)))
618 headSpec = AST.Function (mkVHDLExtId headId) [AST.IfaceVarDec vecPar vectorTM] elemTM
620 headExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
621 (AST.NSimple vecPar) [AST.PrimLit "0"])))
622 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
623 -- return vec(vec'length-1);
624 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
626 [AST.PrimName (AST.NAttribute $
627 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
628 AST.:-: AST.PrimLit "1"])))
629 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
630 -- variable res : fsvec_x (0 to vec'length-2);
633 (AST.SubtypeIn vectorTM
634 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
635 [AST.ToRange (AST.PrimLit "0")
636 (AST.PrimName (AST.NAttribute $
637 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
638 (AST.PrimLit "2")) ]))
640 -- resAST.:= vec(0 to vec'length-2)
641 initExpr = AST.NSimple resId AST.:= (vecSlice
643 (AST.PrimName (AST.NAttribute $
644 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
645 AST.:-: AST.PrimLit "2"))
646 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
647 tailSpec = AST.Function (mkVHDLExtId tailId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
648 -- variable res : fsvec_x (0 to vec'length-2);
651 (AST.SubtypeIn vectorTM
652 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
653 [AST.ToRange (AST.PrimLit "0")
654 (AST.PrimName (AST.NAttribute $
655 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
656 (AST.PrimLit "2")) ]))
658 -- res AST.:= vec(1 to vec'length-1)
659 tailExpr = AST.NSimple resId AST.:= (vecSlice
661 (AST.PrimName (AST.NAttribute $
662 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
663 AST.:-: AST.PrimLit "1"))
664 tailRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
665 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
666 AST.IfaceVarDec vecPar vectorTM ] vectorTM
667 -- variable res : fsvec_x (0 to n-1);
670 (AST.SubtypeIn vectorTM
671 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
672 [AST.ToRange (AST.PrimLit "0")
673 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
674 (AST.PrimLit "1")) ]))
676 -- res AST.:= vec(0 to n-1)
677 takeExpr = AST.NSimple resId AST.:=
678 (vecSlice (AST.PrimLit "1")
679 (AST.PrimName (AST.NSimple $ nPar) AST.:-: AST.PrimLit "1"))
680 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
681 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
682 AST.IfaceVarDec vecPar vectorTM ] vectorTM
683 -- variable res : fsvec_x (0 to vec'length-n-1);
686 (AST.SubtypeIn vectorTM
687 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
688 [AST.ToRange (AST.PrimLit "0")
689 (AST.PrimName (AST.NAttribute $
690 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
691 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
693 -- res AST.:= vec(n to vec'length-1)
694 dropExpr = AST.NSimple resId AST.:= (vecSlice
695 (AST.PrimName $ AST.NSimple nPar)
696 (AST.PrimName (AST.NAttribute $
697 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing)
698 AST.:-: AST.PrimLit "1"))
699 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
700 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
701 AST.IfaceVarDec vecPar vectorTM] vectorTM
702 -- variable res : fsvec_x (0 to vec'length);
705 (AST.SubtypeIn vectorTM
706 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
707 [AST.ToRange (AST.PrimLit "0")
708 (AST.PrimName (AST.NAttribute $
709 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))]))
711 plusgtExpr = AST.NSimple resId AST.:=
712 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
713 (AST.PrimName $ AST.NSimple vecPar))
714 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
715 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
718 (AST.SubtypeIn vectorTM Nothing)
719 (Just $ AST.PrimLit "\"\"")
720 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
721 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
723 -- variable res : fsvec_x (0 to 0) := (others => a);
726 (AST.SubtypeIn vectorTM
727 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
728 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
729 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
730 (AST.PrimName $ AST.NSimple aPar)])
731 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
732 copynSpec = AST.Function (mkVHDLExtId copynId) [AST.IfaceVarDec nPar naturalTM,
733 AST.IfaceVarDec aPar elemTM ] vectorTM
734 -- variable res : fsvec_x (0 to n-1) := (others => a);
737 (AST.SubtypeIn vectorTM
738 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
739 [AST.ToRange (AST.PrimLit "0")
740 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
741 (AST.PrimLit "1")) ]))
742 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
743 (AST.PrimName $ AST.NSimple aPar)])
745 copynExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
746 selSpec = AST.Function (mkVHDLExtId selId) [AST.IfaceVarDec fPar naturalTM,
747 AST.IfaceVarDec sPar naturalTM,
748 AST.IfaceVarDec nPar naturalTM,
749 AST.IfaceVarDec vecPar vectorTM ] vectorTM
750 -- variable res : fsvec_x (0 to n-1);
753 (AST.SubtypeIn vectorTM
754 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
755 [AST.ToRange (AST.PrimLit "0")
756 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
757 (AST.PrimLit "1")) ])
760 -- for i res'range loop
761 -- res(i) := vec(f+i*s);
763 selFor = AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) rangeId Nothing) [selAssign]
764 -- res(i) := vec(f+i*s);
765 selAssign = let origExp = AST.PrimName (AST.NSimple fPar) AST.:+:
766 (AST.PrimName (AST.NSimple iId) AST.:*:
767 AST.PrimName (AST.NSimple sPar)) in
768 AST.NIndexed (AST.IndexedName (AST.NSimple resId) [AST.PrimName (AST.NSimple iId)]) AST.:=
769 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [origExp]))
771 selRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
772 ltplusSpec = AST.Function (mkVHDLExtId ltplusId) [AST.IfaceVarDec vecPar vectorTM,
773 AST.IfaceVarDec aPar elemTM] vectorTM
774 -- variable res : fsvec_x (0 to vec'length);
777 (AST.SubtypeIn vectorTM
778 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
779 [AST.ToRange (AST.PrimLit "0")
780 (AST.PrimName (AST.NAttribute $
781 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))]))
783 ltplusExpr = AST.NSimple resId AST.:=
784 ((AST.PrimName $ AST.NSimple vecPar) AST.:&:
785 (AST.PrimName $ AST.NSimple aPar))
786 ltplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
787 plusplusSpec = AST.Function (mkVHDLExtId plusplusId) [AST.IfaceVarDec vec1Par vectorTM,
788 AST.IfaceVarDec vec2Par vectorTM]
790 -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);
793 (AST.SubtypeIn vectorTM
794 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
795 [AST.ToRange (AST.PrimLit "0")
796 (AST.PrimName (AST.NAttribute $
797 AST.AttribName (AST.NSimple vec1Par) (mkVHDLBasicId lengthId) Nothing) AST.:+:
798 AST.PrimName (AST.NAttribute $
799 AST.AttribName (AST.NSimple vec2Par) (mkVHDLBasicId lengthId) Nothing) AST.:-:
802 plusplusExpr = AST.NSimple resId AST.:=
803 ((AST.PrimName $ AST.NSimple vec1Par) AST.:&:
804 (AST.PrimName $ AST.NSimple vec2Par))
805 plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
806 lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
807 lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $
808 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing))
809 shiftlSpec = AST.Function (mkVHDLExtId shiftlId) [AST.IfaceVarDec vecPar vectorTM,
810 AST.IfaceVarDec aPar elemTM ] vectorTM
811 -- variable res : fsvec_x (0 to vec'length-1);
814 (AST.SubtypeIn vectorTM
815 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
816 [AST.ToRange (AST.PrimLit "0")
817 (AST.PrimName (AST.NAttribute $
818 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
819 (AST.PrimLit "1")) ]))
821 -- res := a & init(vec)
822 shiftlExpr = AST.NSimple resId AST.:=
823 (AST.PrimName (AST.NSimple aPar) AST.:&:
824 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
825 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
826 shiftlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
827 shiftrSpec = AST.Function (mkVHDLExtId shiftrId) [AST.IfaceVarDec vecPar vectorTM,
828 AST.IfaceVarDec aPar elemTM ] vectorTM
829 -- variable res : fsvec_x (0 to vec'length-1);
832 (AST.SubtypeIn vectorTM
833 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
834 [AST.ToRange (AST.PrimLit "0")
835 (AST.PrimName (AST.NAttribute $
836 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
837 (AST.PrimLit "1")) ]))
839 -- res := tail(vec) & a
840 shiftrExpr = AST.NSimple resId AST.:=
841 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
842 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
843 (AST.PrimName (AST.NSimple aPar)))
845 shiftrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
846 nullSpec = AST.Function (mkVHDLExtId nullId) [AST.IfaceVarDec vecPar vectorTM] booleanTM
847 -- return vec'length = 0
848 nullExpr = AST.ReturnSm (Just $
849 AST.PrimName (AST.NAttribute $
850 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:=:
852 rotlSpec = AST.Function (mkVHDLExtId rotlId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
853 -- variable res : fsvec_x (0 to vec'length-1);
856 (AST.SubtypeIn vectorTM
857 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
858 [AST.ToRange (AST.PrimLit "0")
859 (AST.PrimName (AST.NAttribute $
860 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
861 (AST.PrimLit "1")) ]))
863 -- if null(vec) then res := vec else res := last(vec) & init(vec)
864 rotlExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
865 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
866 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
868 (Just $ AST.Else [rotlExprRet])
870 AST.NSimple resId AST.:=
871 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId lastId))
872 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
873 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
874 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
875 rotlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
876 rotrSpec = AST.Function (mkVHDLExtId rotrId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
877 -- variable res : fsvec_x (0 to vec'length-1);
880 (AST.SubtypeIn vectorTM
881 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
882 [AST.ToRange (AST.PrimLit "0")
883 (AST.PrimName (AST.NAttribute $
884 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
885 (AST.PrimLit "1")) ]))
887 -- if null(vec) then res := vec else res := tail(vec) & head(vec)
888 rotrExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
889 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
890 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
892 (Just $ AST.Else [rotrExprRet])
894 AST.NSimple resId AST.:=
895 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
896 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
897 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId headId))
898 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
899 rotrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
900 reverseSpec = AST.Function (mkVHDLExtId reverseId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
903 (AST.SubtypeIn vectorTM
904 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
905 [AST.ToRange (AST.PrimLit "0")
906 (AST.PrimName (AST.NAttribute $
907 AST.AttribName (AST.NSimple vecPar) (mkVHDLBasicId lengthId) Nothing) AST.:-:
908 (AST.PrimLit "1")) ]))
910 -- for i in 0 to res'range loop
911 -- res(vec'length-i-1) := vec(i);
914 AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) rangeId Nothing) [reverseAssign]
915 -- res(vec'length-i-1) := vec(i);
916 reverseAssign = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [destExp]) AST.:=
917 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar)
918 [AST.PrimName $ AST.NSimple iId]))
919 where destExp = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar)
920 (mkVHDLBasicId lengthId) Nothing) AST.:-:
921 AST.PrimName (AST.NSimple iId) AST.:-:
924 reverseRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
926 -----------------------------------------------------------------------------
927 -- A table of builtin functions
928 -----------------------------------------------------------------------------
930 -- | The builtin functions we support. Maps a name to an argument count and a
932 globalNameTable :: NameTable
933 globalNameTable = Map.fromList
934 [ (exId , (2, genFCall False ) )
935 , (replaceId , (3, genFCall False ) )
936 , (headId , (1, genFCall True ) )
937 , (lastId , (1, genFCall True ) )
938 , (tailId , (1, genFCall False ) )
939 , (initId , (1, genFCall False ) )
940 , (takeId , (2, genFCall False ) )
941 , (dropId , (2, genFCall False ) )
942 , (selId , (4, genFCall False ) )
943 , (plusgtId , (2, genFCall False ) )
944 , (ltplusId , (2, genFCall False ) )
945 , (plusplusId , (2, genFCall False ) )
946 , (mapId , (2, genMap ) )
947 , (zipWithId , (3, genZipWith ) )
948 , (foldlId , (3, genFoldl ) )
949 , (foldrId , (3, genFoldr ) )
950 , (zipId , (2, genZip ) )
951 , (unzipId , (1, genUnzip ) )
952 , (shiftlId , (2, genFCall False ) )
953 , (shiftrId , (2, genFCall False ) )
954 , (rotlId , (1, genFCall False ) )
955 , (rotrId , (1, genFCall False ) )
956 , (concatId , (1, genConcat ) )
957 , (reverseId , (1, genFCall False ) )
958 , (iteratenId , (3, genIteraten ) )
959 , (iterateId , (2, genIterate ) )
960 , (generatenId , (3, genGeneraten ) )
961 , (generateId , (2, genGenerate ) )
962 , (emptyId , (0, genFCall False ) )
963 , (singletonId , (1, genFCall False ) )
964 , (copynId , (2, genFCall False ) )
965 , (copyId , (1, genCopy ) )
966 , (lengthTId , (1, genFCall False ) )
967 , (nullId , (1, genFCall False ) )
968 , (hwxorId , (2, genOperator2 AST.Xor ) )
969 , (hwandId , (2, genOperator2 AST.And ) )
970 , (hworId , (2, genOperator2 AST.Or ) )
971 , (hwnotId , (1, genOperator1 AST.Not ) )
972 , (plusId , (2, genOperator2 (AST.:+:) ) )
973 , (timesId , (2, genOperator2 (AST.:*:) ) )
974 , (negateId , (1, genOperator1 AST.Neg ) )
975 , (minusId , (2, genOperator2 (AST.:-:) ) )
976 , (fromSizedWordId , (1, genFromSizedWord ) )
977 , (fromIntegerId , (1, genFromInteger ) )