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Learn ExpandExpr how to handle simple case expressions.
2009-01-29 Matthijs KooijmanLearn ExpandExpr how to handle simple case expressions.
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2009-01-29 Matthijs KooijmanAdd a base case to splitTupleConstructorArgs.
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2009-01-29 Matthijs KooijmanLearn expandExpr how to handle tuple construction.
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2009-01-29 Matthijs KooijmanAdd a duplication hardware model.
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2009-01-29 Matthijs KooijmanImplement expandArgs in terms of expandExpr.
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2009-01-29 Matthijs KooijmanAdd a double invertor model.
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2009-01-29 Matthijs KooijmanLearn expandExpr how to expand Application.
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2009-01-29 Matthijs KooijmanLet expandExpr error out on unsupported expressions.
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2009-01-29 Matthijs KooijmanAdd an invertor hardware model.
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2009-01-29 Matthijs KooijmanRework the VHDL generation to be more bottom up.
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2009-01-29 Matthijs KooijmanAdd a trivial "wire" hardware model.
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2009-01-29 Matthijs KooijmanRename PortNameMap to SignalNameMap and make it a dependent...
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2009-01-29 Matthijs KooijmanMove around some functionality.
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2009-01-29 Matthijs KooijmanReorder and comment things a bit.
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2009-01-29 Matthijs KooijmanUse uniqueName to make component instantiations unique.
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2009-01-29 Matthijs KooijmanAdd a uniqueName function.
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2009-01-29 Matthijs KooijmanAdd some comments.
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2009-01-27 Matthijs KooijmanUse spaces instead of tabs.
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2009-01-27 Matthijs KooijmanPut getInstantiations in the State monad.
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2009-01-27 Matthijs KooijmanPut getArchitecture inside the State monad.
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2009-01-27 Matthijs KooijmanMake the state monad calling code more pretty.
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2009-01-27 Matthijs KooijmanRun mkHWFunction and addFunc in a State monad.
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2009-01-27 Matthijs KooijmanDerive Show for the data types we define.
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2009-01-22 Matthijs KooijmanRemove the Args constructor, just use a list instead.
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2009-01-22 Matthijs KooijmanLook up the port names in the session when generating...
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2009-01-22 Matthijs KooijmanGenerate a HWFunction for the function that is being...
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2009-01-22 Matthijs KooijmanLookup input port names for instantiations in the session.
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2009-01-22 Matthijs KooijmanMake getPortMapEntry accept a PortNameMap.
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2009-01-22 Matthijs KooijmanPass around a session variable.
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2009-01-22 Matthijs KooijmanUse ForSyDe.Backend.VHDL modules to generate VHDL.
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2009-01-22 Matthijs KooijmanRemove the entity generation code.
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2009-01-21 Matthijs KooijmanHandle tuple constructors in expressions.
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2009-01-21 Matthijs KooijmanLet the Adders module export everything.
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2009-01-21 Matthijs KooijmanAdd a haskell model for a half adder.
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2009-01-21 Matthijs KooijmanAdd an error message.
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2009-01-21 Matthijs KooijmanMap output ports as well as input ports.
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2009-01-21 Matthijs KooijmanGenerate input port names from the argument types.
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2009-01-19 Matthijs KooijmanAdd .gitignore file.
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2009-01-19 Matthijs KooijmanIntial import of some haskell programs.
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The Cλash compiler