Add a is_FApp predicate.

diff --git a/FlattenTypes.hs b/FlattenTypes.hs
index 44879d00b6683d3c54d6965aab736984091c9e6a..b7be4645d89e1df519487192268d48d4ab6e978c 100644 (file)
--- a/FlattenTypes.hs
+++ b/FlattenTypes.hs
@@ -96,6 +96,12 @@ data SigDef =
     defDst :: SignalId
   } deriving (Show, Eq)
 
+-- | Is the given SigDef a FApp?
+is_FApp :: SigDef -> Bool
+is_FApp d = case d of  
+  (FApp _ _ _) -> True
+  _ -> False
+
 -- | An expression on signals
 data SignalExpr = 
   EqLit SignalId String -- ^ Is the given signal equal to the given (VHDL) literal