From db63e913f56b427533d29327b25a14b6b75b6d79 Mon Sep 17 00:00:00 2001
From: Matthijs Kooijman <matthijs@stdin.nl>
Date: Tue, 3 Mar 2009 12:21:35 +0100
Subject: [PATCH] Add a is_FApp predicate.

---
 FlattenTypes.hs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/FlattenTypes.hs b/FlattenTypes.hs
index 44879d0..b7be464 100644
--- a/FlattenTypes.hs
+++ b/FlattenTypes.hs
@@ -96,6 +96,12 @@ data SigDef =
     defDst :: SignalId
   } deriving (Show, Eq)
 
+-- | Is the given SigDef a FApp?
+is_FApp :: SigDef -> Bool
+is_FApp d = case d of  
+  (FApp _ _ _) -> True
+  _ -> False
+
 -- | An expression on signals
 data SignalExpr = 
   EqLit SignalId String -- ^ Is the given signal equal to the given (VHDL) literal
-- 
2.30.2