import qualified Type
import HsValueMap
+import CoreShow
-- | A signal identifier
type SignalId = Int
| SigStateOld StateId -- | Use as the current internal state
| SigStateNew StateId -- | Use as the new internal state
| SigSubState -- | Do not use, state variable is used in a subcircuit
+ deriving (Show)
-- | Is this a port signal use?
isPortSigUse :: SigUse -> Bool
sigUse :: SigUse,
sigTy :: Type.Type,
nameHints :: [String]
-}
+} deriving (Show)
-- | A flattened function
data FlatFunction = FlatFunction {
flat_res :: SignalMap,
flat_defs :: [SigDef],
flat_sigs :: [(SignalId, SignalInfo)]
-}
+} deriving (Show)
-- | Lookup a given signal id in a signal map, and return the associated
-- SignalInfo. Errors out if the signal was not found.
flatFunc :: Maybe FlatFunction,
funcEntity :: Maybe Entity,
funcArch :: Maybe AST.ArchBody
-}
+} deriving (Show)
data VHDLSession = VHDLSession {
coreMod :: HscTypes.CoreModule, -- The current module
ent_res :: VHDLSignalMap, -- A mapping of the function result to port names
ent_decl :: Maybe AST.EntityDec, -- The actual entity declaration. Can be empty for builtin functions.
ent_pkg_decl :: Maybe AST.PackageDec -- A package declaration with types for this entity
-}
+} deriving (Show);