Partly fixed implementation for integer literals.

But it still needs alot of fixing

diff --git a/Adders.hs b/Adders.hs
index cba5afed96519bb7c06f0c804b2fa0ed68de1593..d9c1d26f61be295d5061654608616117c31c2ac2 100644 (file)
--- a/Adders.hs
+++ b/Adders.hs
@@ -178,8 +178,8 @@ highordtest = \x ->
 
 xand a b = hwand a b
 
-functiontest :: SizedInt D8 -> SizedInt D8
-functiontest = \a -> let r = a + (1 :: SizedInt D8) in r
+functiontest :: SizedWord D8 -> SizedWord D8
+functiontest = \a -> let r = a + ((-1) :: SizedWord D8) in r
 
 xhwnot x = hwnot x
 

diff --git a/Constants.hs b/Constants.hs
index 838f9c5cb3567e8f44dc05c0e600c747b4574ab7..c392521becb7817da215ee3ad379d976f6b80842 100644 (file)
--- a/Constants.hs
+++ b/Constants.hs
@@ -252,6 +252,12 @@ toIntegerId = "to_integer"
 fromIntegerId :: String
 fromIntegerId = "fromInteger"
 
+toSignedId :: String
+toSignedId = "to_signed"
+
+toUnsignedId :: String
+toUnsignedId = "to_unsigned"
+
 ------------------
 -- VHDL type marks
 ------------------

diff --git a/Generate.hs b/Generate.hs
index bd7b482714438a63834234d95433a643b5a08248..947c22254a7a1369b86bcd25d6918cfe6a12523e 100644 (file)
--- a/Generate.hs
+++ b/Generate.hs
@@ -18,6 +18,8 @@ import Type
 import qualified Var
 import qualified IdInfo
 import qualified Literal
+import qualified Name
+import qualified TyCon
 
 -- Local imports
 import Constants
@@ -110,8 +112,20 @@ genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cann
 genFromInteger :: BuiltinBuilder
 genFromInteger = genLitArgs $ genExprRes genFromInteger'
 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> VHDLSession AST.Expr
-genFromInteger' (Left res) f args = do
-  return $ AST.PrimLit (pprString (last args))
+genFromInteger' (Left res) f lits = 
+  return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname)) 
+            [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
+  where
+  ty = Var.varType res
+  (tycon, args) = Type.splitTyConApp ty
+  name = Name.getOccString (TyCon.tyConName tycon)
+  len = case name of
+    "SizedInt" -> sized_int_len ty
+    "SizedWord" -> sized_word_len ty
+  fname = case name of
+    "SizedInt" -> toSignedId
+    "SizedWord" -> toUnsignedId
+
 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
 
 
@@ -957,7 +971,7 @@ globalNameTable = Map.fromList
   , (hwnotId          , (1, genOperator1 AST.Not    ) )
   , (plusId           , (2, genOperator2 (AST.:+:)  ) )
   , (timesId          , (2, genOperator2 (AST.:*:)  ) )
-  , (negateId         , (1, genOperator1 AST.Not    ) )
+  , (negateId         , (1, genOperator1 AST.Neg    ) )
   , (minusId          , (2, genOperator2 (AST.:-:)  ) )
   , (fromSizedWordId  , (1, genFromSizedWord        ) )
   , (fromIntegerId    , (1, genFromInteger          ) )