preamble.aux
reducer.aux
summery.aux
+PolyAlu
+upload.sh
+vhdl
{-# LINE 4 "PolyAlu.lhs" #-}
{-# LANGUAGE TypeOperators, TypeFamilies, FlexibleContexts #-}
-module PolyCPU where
+module Main where
import qualified Prelude as P
-{-# LINE 27 "PolyAlu.lhs" #-}
+{-# LINE 29 "PolyAlu.lhs" #-}
import CLasH.HardwareTypes
+{-# LINE 36 "PolyAlu.lhs" #-}
import CLasH.Translator.Annotations
-{-# LINE 37 "PolyAlu.lhs" #-}
+{-# LINE 48 "PolyAlu.lhs" #-}
type Op s a = a -> Vector s a -> a
type Opcode = Bit
-{-# LINE 42 "PolyAlu.lhs" #-}
+{-# LINE 56 "PolyAlu.lhs" #-}
type RegBank s a = Vector (s :+: D1) a
type RegState s a = State (RegBank s a)
-{-# LINE 47 "PolyAlu.lhs" #-}
+{-# LINE 64 "PolyAlu.lhs" #-}
type Word = SizedInt D12
-{-# LINE 55 "PolyAlu.lhs" #-}
+{-# LINE 76 "PolyAlu.lhs" #-}
primOp :: (a -> a -> a) -> Op s a
primOp f a b = a `f` a
-{-# LINE 60 "PolyAlu.lhs" #-}
+{-# LINE 84 "PolyAlu.lhs" #-}
vectOp :: (a -> a -> a) -> Op s a
vectOp f a b = foldl f a b
-{-# LINE 69 "PolyAlu.lhs" #-}
+{-# LINE 96 "PolyAlu.lhs" #-}
alu ::
Op s a ->
Op s a ->
Opcode -> a -> Vector s a -> a
alu op1 op2 Low a b = op1 a b
alu op1 op2 High a b = op2 a b
-{-# LINE 82 "PolyAlu.lhs" #-}
+{-# LINE 112 "PolyAlu.lhs" #-}
registerBank ::
((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
(RegState s a) -> a -> RangedWord s ->
((State mem'), data_out)
where
data_out = mem!rdaddr
- mem' | wrenable == Low = mem
- | otherwise = replace mem wraddr data_in
-{-# LINE 100 "PolyAlu.lhs" #-}
+ mem' | wrenable == Low = mem
+ | otherwise = replace mem wraddr data_in
+{-# LINE 133 "PolyAlu.lhs" #-}
{-# ANN actual_cpu TopEntity#-}
actual_cpu ::
- (Opcode, Word, Vector D4 Word,
- RangedWord D9,
- RangedWord D9, Bit) ->
- RegState D9 Word ->
+ (Opcode, Word, Vector D4 Word, RangedWord D9,
+ RangedWord D9, Bit) -> RegState D9 Word ->
(RegState D9 Word, Word)
actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
where
- alu_out = alu simpleOp vectorOp opc ram_out b
+ alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b
(ram',ram_out) = registerBank ram a rdaddr wraddr wren
- simpleOp = primOp (+)
- vectorOp = vectOp (+)
+{-# LINE 149 "PolyAlu.lhs" #-}
+{-# ANN initstate InitState#-}
+initstate :: RegState D9 Word
+initstate = State (copy (0 :: Word))
+
+{-# ANN program TestInput#-}
+program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)]
+program =
+ [ (Low, 4, copy (0::Word), 0, 0, High) -- Write 4 to Reg0, out = 0
+ , (Low, 3, copy (0::Word), 0, 1, High) -- Write 3 to Reg1, out = Reg0 + Reg0 = 8
+ , (High,0, copy (3::Word), 1, 0, Low) -- No Write , out = 15
+ ]
+
+run func state [] = []
+run func state (i:input) = o:out
+ where
+ (state', o) = func i state
+ out = run func state' input
+
+main :: IO ()
+main = do
+ let input = program
+ let istate = initstate
+ let output = run actual_cpu istate input
+ mapM_ (\x -> putStr $ ("# (" P.++ (show x) P.++ ")\n")) output
+ return ()
%if style == newcode
\begin{code}
{-# LANGUAGE TypeOperators, TypeFamilies, FlexibleContexts #-}
-module PolyCPU where
+module Main where
import qualified Prelude as P
\end{code}
{
\frametitle{Imports}
Import all the built-in types, such as vectors and integers:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
import CLasH.HardwareTypes
-\end{code}\pause
+\end{code}
+\end{beamercolorbox}\pause
+
Import annotations, helps \clash{} to find top-level component:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
import CLasH.Translator.Annotations
\end{code}
+\end{beamercolorbox}
}
\subsection{Type Definitions}
\frame
{
+\frametitle{Type definitions}
First we define some ALU types:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
type Op s a = a -> Vector s a -> a
type Opcode = Bit
-\end{code}\pause
+\end{code}
+\end{beamercolorbox}\pause
+
And some Register types:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
type RegBank s a = Vector (s :+: D1) a
type RegState s a = State (RegBank s a)
-\end{code}\pause
+\end{code}
+\end{beamercolorbox}\pause
+
And a simple Word type:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
type Word = SizedInt D12
\end{code}
+\end{beamercolorbox}
}
+
\subsection{Frameworks for Operations}
\frame
{
+\frametitle{Operations}
We make a primitive operation:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
primOp :: {-"{\color<3>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
primOp f a b = a `f` a
-\end{code}\pause
+\end{code}
+\end{beamercolorbox}\pause
+
We make a vector operation:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
vectOp :: {-"{\color<3>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a
vectOp f a b = {-"{\color<3>[rgb]{1,0,0}"-}foldl{-"}"-} f a b
\end{code}
+\end{beamercolorbox}
+\begin{itemize}
+\uncover<3->{\item We support Higher-Order Functionality}
+\end{itemize}
}
\subsection{Polymorphic, Higher-Order ALU}
\frame
{
+\frametitle{Simple ALU}
We define a polymorphic ALU:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
alu ::
Op s a ->
alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}Low{-"}"-} a b = op1 a b
alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b
\end{code}
+\end{beamercolorbox}
+\begin{itemize}
+\uncover<2->{\item We support Patter Matching}
+\end{itemize}
}
\subsection{Register bank}
\frame
{
+\frametitle{Register Bank}
Make a simple register bank:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
registerBank ::
- CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) =>
- (RegState s a) -> a -> RangedWord s ->
+ CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s ->
RangedWord s -> Bit -> ((RegState s a), a )
registerBank (State mem) data_in rdaddr wraddr wrenable =
mem' {-"{\color<2>[rgb]{1,0,0}"-}| wrenable == Low{-"}"-} = mem
{-"{\color<2>[rgb]{1,0,0}"-}| otherwise{-"}"-} = replace mem wraddr data_in
\end{code}
+\end{beamercolorbox}
+\begin{itemize}
+\uncover<2->{\item We support Guards}
+\end{itemize}
}
\subsection{Simple CPU: ALU \& Register Bank}
\frame
{
+\frametitle{Simple CPU}
Combining ALU and register bank:
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
{-"{\color<2>[rgb]{1,0,0}"-}ANN(actual_cpu TopEntity){-"}"-}
actual_cpu ::
RangedWord D9, Bit) -> RegState D9 Word ->
(RegState D9 Word, Word)
-actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram =
- (ram', alu_out)
+actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out)
where
- alu_out = alu simpleOp vectorOp opc ram_out b
+ alu_out = alu ({-"{\color<3>[rgb]{1,0,0}"-}primOp (+){-"}"-}) ({-"{\color<3>[rgb]{1,0,0}"-}vectOp (+){-"}"-}) opc ram_out b
(ram',ram_out) = registerBank ram a rdaddr wraddr wren
- simpleOp = primOp (+)
- vectorOp = vectOp (+)
\end{code}
+\end{beamercolorbox}
+\begin{itemize}
+\uncover<2->{\item Annotation is used to indicate top-level component}
+\end{itemize}
}
+
+%if style == newcode
+\begin{code}
+ANN(initstate InitState)
+initstate :: RegState D9 Word
+initstate = State (copy (0 :: Word))
+
+ANN(program TestInput)
+program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)]
+program =
+ [ (Low, 4, copy (0::Word), 0, 0, High) -- Write 4 to Reg0, out = 0
+ , (Low, 3, copy (0::Word), 0, 1, High) -- Write 3 to Reg1, out = Reg0 + Reg0 = 8
+ , (High,0, copy (3::Word), 1, 0, Low) -- No Write , out = 15
+ ]
+
+run func state [] = []
+run func state (i:input) = o:out
+ where
+ (state', o) = func i state
+ out = run func state' input
+
+main :: IO ()
+main = do
+ let input = program
+ let istate = initstate
+ let output = run actual_cpu istate input
+ mapM_ (\x -> putStr $ ("# (" P.++ (show x) P.++ ")\n")) output
+ return ()
+\end{code}
+%endif
\ No newline at end of file
\setbeamercolor{itemize subitem}{fg=ut_green}
\setbeamercolor{itemize subsubitem}{fg=ut_blue}
+\colorlet{ut_light}{ut_blue!10!white}
+\setbeamercolor{codebox}{bg=ut_light,fg=ut_blue}
+
\mode
<all>
\DeclareOption*{\PassOptionsToClass{\CurrentOption}{beamer}}\r
%\DeclareOption*{\PassOptionsToClass{\CurrentOption}{beamer}}\r
\ProcessOptions\relax\r
-\LoadClass[t,12pt,hyperref={unicode},notes=show]{beamer}\r
+\LoadClass[t,11pt,hyperref={unicode},notes=show]{beamer}\r
\r
\pdfpageattr {/Group << /S /Transparency /I true /CS /DeviceRGB>>} %Solves colorshift due to transparency in figures\r
\RequirePackage{tikz}\r
\item No Effort:\\
GHC API Parses, Typechecks and Desugars Haskell \pause
\item Hard.. sort of: \\
- Transform resulting Core, GHC's Intermediate Language, to a normal form \pause
+ Transform resulting Core, GHC's Intermediate Language,\linebreak to a normal form \pause
\item Easy: \\
Translate Normalized Core to synthesizable VHDL
\end{itemize}
\frame
{
\frametitle{Haskell Description}
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
mealyMachine ::
InputSignals ->
{-"{\color<3>[rgb]{1,0,0}"-}new_state{-"}"-} = logic {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} input
outputs = logic {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} input
\end{code}
+\end{beamercolorbox}
}
\subsection{Simulation}
\frame
{
\frametitle{Simulating a Mealy Machine}
+\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox}
\begin{code}
run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} [] = []
run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} (i:input) = o:out
where
- ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o) = func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} i
+ ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o) = func i {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-}
out = run func {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input
\end{code}
+\end{beamercolorbox}
}
\ No newline at end of file
\usepackage[english]{babel}
+\usepackage{xcolor}
\newcommand{\clash}[0]{C$\lambda$asH}
\ No newline at end of file
projects / matthijs / master-project / haskell-symposium-talk.git / commitdiff