From: Christiaan Baaij Date: Wed, 26 Aug 2009 09:27:32 +0000 (+0200) Subject: Put code in colored boxes X-Git-Url: https://git.stderr.nl/gitweb?p=matthijs%2Fmaster-project%2Fhaskell-symposium-talk.git;a=commitdiff_plain;h=994fb60ca2fb9a48380e54b4392f7519fcc63ec1 Put code in colored boxes --- diff --git a/.gitignore b/.gitignore index 8dd6345..ba69556 100644 --- a/.gitignore +++ b/.gitignore @@ -16,3 +16,6 @@ mealymachine.pdf preamble.aux reducer.aux summery.aux +PolyAlu +upload.sh +vhdl diff --git a/PolyAlu.hs b/PolyAlu.hs index afe9f5d..23dfaa4 100644 --- a/PolyAlu.hs +++ b/PolyAlu.hs @@ -1,33 +1,34 @@ {-# LINE 4 "PolyAlu.lhs" #-} {-# LANGUAGE TypeOperators, TypeFamilies, FlexibleContexts #-} -module PolyCPU where +module Main where import qualified Prelude as P -{-# LINE 27 "PolyAlu.lhs" #-} +{-# LINE 29 "PolyAlu.lhs" #-} import CLasH.HardwareTypes +{-# LINE 36 "PolyAlu.lhs" #-} import CLasH.Translator.Annotations -{-# LINE 37 "PolyAlu.lhs" #-} +{-# LINE 48 "PolyAlu.lhs" #-} type Op s a = a -> Vector s a -> a type Opcode = Bit -{-# LINE 42 "PolyAlu.lhs" #-} +{-# LINE 56 "PolyAlu.lhs" #-} type RegBank s a = Vector (s :+: D1) a type RegState s a = State (RegBank s a) -{-# LINE 47 "PolyAlu.lhs" #-} +{-# LINE 64 "PolyAlu.lhs" #-} type Word = SizedInt D12 -{-# LINE 55 "PolyAlu.lhs" #-} +{-# LINE 76 "PolyAlu.lhs" #-} primOp :: (a -> a -> a) -> Op s a primOp f a b = a `f` a -{-# LINE 60 "PolyAlu.lhs" #-} +{-# LINE 84 "PolyAlu.lhs" #-} vectOp :: (a -> a -> a) -> Op s a vectOp f a b = foldl f a b -{-# LINE 69 "PolyAlu.lhs" #-} +{-# LINE 96 "PolyAlu.lhs" #-} alu :: Op s a -> Op s a -> Opcode -> a -> Vector s a -> a alu op1 op2 Low a b = op1 a b alu op1 op2 High a b = op2 a b -{-# LINE 82 "PolyAlu.lhs" #-} +{-# LINE 112 "PolyAlu.lhs" #-} registerBank :: ((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s -> @@ -37,20 +38,42 @@ registerBank (State mem) data_in rdaddr wraddr wrenable = ((State mem'), data_out) where data_out = mem!rdaddr - mem' | wrenable == Low = mem - | otherwise = replace mem wraddr data_in -{-# LINE 100 "PolyAlu.lhs" #-} + mem' | wrenable == Low = mem + | otherwise = replace mem wraddr data_in +{-# LINE 133 "PolyAlu.lhs" #-} {-# ANN actual_cpu TopEntity#-} actual_cpu :: - (Opcode, Word, Vector D4 Word, - RangedWord D9, - RangedWord D9, Bit) -> - RegState D9 Word -> + (Opcode, Word, Vector D4 Word, RangedWord D9, + RangedWord D9, Bit) -> RegState D9 Word -> (RegState D9 Word, Word) actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out) where - alu_out = alu simpleOp vectorOp opc ram_out b + alu_out = alu (primOp (+)) (vectOp (+)) opc ram_out b (ram',ram_out) = registerBank ram a rdaddr wraddr wren - simpleOp = primOp (+) - vectorOp = vectOp (+) +{-# LINE 149 "PolyAlu.lhs" #-} +{-# ANN initstate InitState#-} +initstate :: RegState D9 Word +initstate = State (copy (0 :: Word)) + +{-# ANN program TestInput#-} +program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)] +program = + [ (Low, 4, copy (0::Word), 0, 0, High) -- Write 4 to Reg0, out = 0 + , (Low, 3, copy (0::Word), 0, 1, High) -- Write 3 to Reg1, out = Reg0 + Reg0 = 8 + , (High,0, copy (3::Word), 1, 0, Low) -- No Write , out = 15 + ] + +run func state [] = [] +run func state (i:input) = o:out + where + (state', o) = func i state + out = run func state' input + +main :: IO () +main = do + let input = program + let istate = initstate + let output = run actual_cpu istate input + mapM_ (\x -> putStr $ ("# (" P.++ (show x) P.++ ")\n")) output + return () diff --git a/PolyAlu.lhs b/PolyAlu.lhs index 55b000d..5a4e26a 100644 --- a/PolyAlu.lhs +++ b/PolyAlu.lhs @@ -2,7 +2,7 @@ %if style == newcode \begin{code} {-# LANGUAGE TypeOperators, TypeFamilies, FlexibleContexts #-} -module PolyCPU where +module Main where import qualified Prelude as P \end{code} @@ -24,51 +24,77 @@ import qualified Prelude as P { \frametitle{Imports} Import all the built-in types, such as vectors and integers: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} import CLasH.HardwareTypes -\end{code}\pause +\end{code} +\end{beamercolorbox}\pause + Import annotations, helps \clash{} to find top-level component: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} import CLasH.Translator.Annotations \end{code} +\end{beamercolorbox} } \subsection{Type Definitions} \frame { +\frametitle{Type definitions} First we define some ALU types: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} type Op s a = a -> Vector s a -> a type Opcode = Bit -\end{code}\pause +\end{code} +\end{beamercolorbox}\pause + And some Register types: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} type RegBank s a = Vector (s :+: D1) a type RegState s a = State (RegBank s a) -\end{code}\pause +\end{code} +\end{beamercolorbox}\pause + And a simple Word type: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} type Word = SizedInt D12 \end{code} +\end{beamercolorbox} } + \subsection{Frameworks for Operations} \frame { +\frametitle{Operations} We make a primitive operation: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} primOp :: {-"{\color<3>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a primOp f a b = a `f` a -\end{code}\pause +\end{code} +\end{beamercolorbox}\pause + We make a vector operation: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} vectOp :: {-"{\color<3>[rgb]{1,0,0}"-}(a -> a -> a){-"}"-} -> Op s a vectOp f a b = {-"{\color<3>[rgb]{1,0,0}"-}foldl{-"}"-} f a b \end{code} +\end{beamercolorbox} +\begin{itemize} +\uncover<3->{\item We support Higher-Order Functionality} +\end{itemize} } \subsection{Polymorphic, Higher-Order ALU} \frame { +\frametitle{Simple ALU} We define a polymorphic ALU: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} alu :: Op s a -> @@ -77,15 +103,20 @@ alu :: alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}Low{-"}"-} a b = op1 a b alu op1 op2 {-"{\color<2>[rgb]{1,0,0}"-}High{-"}"-} a b = op2 a b \end{code} +\end{beamercolorbox} +\begin{itemize} +\uncover<2->{\item We support Patter Matching} +\end{itemize} } \subsection{Register bank} \frame { +\frametitle{Register Bank} Make a simple register bank: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} registerBank :: - CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => - (RegState s a) -> a -> RangedWord s -> + CXT((NaturalT s ,PositiveT (s :+: D1),((s :+: D1) :>: s) ~ True )) => (RegState s a) -> a -> RangedWord s -> RangedWord s -> Bit -> ((RegState s a), a ) registerBank (State mem) data_in rdaddr wraddr wrenable = @@ -95,11 +126,17 @@ registerBank (State mem) data_in rdaddr wraddr wrenable = mem' {-"{\color<2>[rgb]{1,0,0}"-}| wrenable == Low{-"}"-} = mem {-"{\color<2>[rgb]{1,0,0}"-}| otherwise{-"}"-} = replace mem wraddr data_in \end{code} +\end{beamercolorbox} +\begin{itemize} +\uncover<2->{\item We support Guards} +\end{itemize} } \subsection{Simple CPU: ALU \& Register Bank} \frame { +\frametitle{Simple CPU} Combining ALU and register bank: +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} {-"{\color<2>[rgb]{1,0,0}"-}ANN(actual_cpu TopEntity){-"}"-} actual_cpu :: @@ -107,12 +144,43 @@ actual_cpu :: RangedWord D9, Bit) -> RegState D9 Word -> (RegState D9 Word, Word) -actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = - (ram', alu_out) +actual_cpu (opc, a ,b, rdaddr, wraddr, wren) ram = (ram', alu_out) where - alu_out = alu simpleOp vectorOp opc ram_out b + alu_out = alu ({-"{\color<3>[rgb]{1,0,0}"-}primOp (+){-"}"-}) ({-"{\color<3>[rgb]{1,0,0}"-}vectOp (+){-"}"-}) opc ram_out b (ram',ram_out) = registerBank ram a rdaddr wraddr wren - simpleOp = primOp (+) - vectorOp = vectOp (+) \end{code} +\end{beamercolorbox} +\begin{itemize} +\uncover<2->{\item Annotation is used to indicate top-level component} +\end{itemize} } + +%if style == newcode +\begin{code} +ANN(initstate InitState) +initstate :: RegState D9 Word +initstate = State (copy (0 :: Word)) + +ANN(program TestInput) +program :: [(Opcode, Word, Vector D4 Word, RangedWord D9, RangedWord D9, Bit)] +program = + [ (Low, 4, copy (0::Word), 0, 0, High) -- Write 4 to Reg0, out = 0 + , (Low, 3, copy (0::Word), 0, 1, High) -- Write 3 to Reg1, out = Reg0 + Reg0 = 8 + , (High,0, copy (3::Word), 1, 0, Low) -- No Write , out = 15 + ] + +run func state [] = [] +run func state (i:input) = o:out + where + (state', o) = func i state + out = run func state' input + +main :: IO () +main = do + let input = program + let istate = initstate + let output = run actual_cpu istate input + mapM_ (\x -> putStr $ ("# (" P.++ (show x) P.++ ")\n")) output + return () +\end{code} +%endif \ No newline at end of file diff --git a/beamercolorthemecaes.sty b/beamercolorthemecaes.sty index b36c1a3..48617c5 100644 --- a/beamercolorthemecaes.sty +++ b/beamercolorthemecaes.sty @@ -35,5 +35,8 @@ \setbeamercolor{itemize subitem}{fg=ut_green} \setbeamercolor{itemize subsubitem}{fg=ut_blue} +\colorlet{ut_light}{ut_blue!10!white} +\setbeamercolor{codebox}{bg=ut_light,fg=ut_blue} + \mode diff --git a/caes_presentation.cls b/caes_presentation.cls index 599def2..61ff482 100644 --- a/caes_presentation.cls +++ b/caes_presentation.cls @@ -26,7 +26,7 @@ \DeclareOption*{\PassOptionsToClass{\CurrentOption}{beamer}} %\DeclareOption*{\PassOptionsToClass{\CurrentOption}{beamer}} \ProcessOptions\relax -\LoadClass[t,12pt,hyperref={unicode},notes=show]{beamer} +\LoadClass[t,11pt,hyperref={unicode},notes=show]{beamer} \pdfpageattr {/Group << /S /Transparency /I true /CS /DeviceRGB>>} %Solves colorshift due to transparency in figures \RequirePackage{tikz} diff --git a/clash-haskell09.pdf b/clash-haskell09.pdf index 051f90d..19fe325 100644 Binary files a/clash-haskell09.pdf and b/clash-haskell09.pdf differ diff --git a/howdoesitwork.lhs b/howdoesitwork.lhs index f073c8a..39137bd 100644 --- a/howdoesitwork.lhs +++ b/howdoesitwork.lhs @@ -8,7 +8,7 @@ \item No Effort:\\ GHC API Parses, Typechecks and Desugars Haskell \pause \item Hard.. sort of: \\ - Transform resulting Core, GHC's Intermediate Language, to a normal form \pause + Transform resulting Core, GHC's Intermediate Language,\linebreak to a normal form \pause \item Easy: \\ Translate Normalized Core to synthesizable VHDL \end{itemize} diff --git a/introduction.lhs b/introduction.lhs index 5cd6c0a..32afbe9 100644 --- a/introduction.lhs +++ b/introduction.lhs @@ -46,6 +46,7 @@ Voor wie het niet meer weet, dit is een mealy machine \frame { \frametitle{Haskell Description} +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} mealyMachine :: InputSignals -> @@ -56,16 +57,19 @@ mealyMachine inputs {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} = ({-"{\color<3>[rg {-"{\color<3>[rgb]{1,0,0}"-}new_state{-"}"-} = logic {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} input outputs = logic {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} input \end{code} +\end{beamercolorbox} } \subsection{Simulation} \frame { \frametitle{Simulating a Mealy Machine} +\begin{beamercolorbox}[sep=-2.5ex,rounded=true,shadow=true,vmode]{codebox} \begin{code} run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} [] = [] run func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} (i:input) = o:out where - ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o) = func {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} i + ({-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-}, o) = func i {-"{\color<2>[rgb]{1,0,0}"-}state{-"}"-} out = run func {-"{\color<3>[rgb]{1,0,0}"-}state'{-"}"-} input \end{code} +\end{beamercolorbox} } \ No newline at end of file diff --git a/preamble.tex b/preamble.tex index b8efa6a..20c6a89 100644 --- a/preamble.tex +++ b/preamble.tex @@ -1,3 +1,4 @@ \usepackage[english]{babel} +\usepackage{xcolor} \newcommand{\clash}[0]{C$\lambda$asH} \ No newline at end of file