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Generate a VHDL architecture for each function.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 13:45:05 +0000 (14:45 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Fri, 13 Feb 2009 13:45:05 +0000 (14:45 +0100)
The architecture contains signal declarations, but no instantiations yet.


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The Cλash compiler