}
}
-
\define[3]\transexample{
\placeexample[here]{#1}
\startcombination[2*1]
{\example{#3}}{Transformed program}
\stopcombination
}
-%
-%\define[3]\transexampleh{
-%% \placeexample[here]{#1}
-%% \startcombination[1*2]
-%% {\example{#2}}{Original program}
-%% {\example{#3}}{Transformed program}
-%% \stopcombination
-%}
The first step in the core to \small{VHDL} translation process, is normalization. We
aim to bring the core description into a simpler form, which we can