Rename eitherCoreOrExprArgs to argsToVHDLExprs.

Also add a helper function to make it more readable.

diff --git a/cλash/CLasH/VHDL/Generate.hs b/cλash/CLasH/VHDL/Generate.hs
index 0b2cf04d6b2e171b459186607aa3530a203c7060..31c9c8d7f11f192eb5f12b68030579cf50caf567 100644 (file)
--- a/cλash/CLasH/VHDL/Generate.hs
+++ b/cλash/CLasH/VHDL/Generate.hs
@@ -199,11 +199,16 @@ mkConcSm (bndr, expr) = error $ "\nVHDL.mkConcSM: Unsupported binding in let exp
 -- | A function to wrap a builder-like function that expects its arguments to
 -- be expressions.
 genExprArgs wrap dst func args = do
-  args' <- eitherCoreOrExprArgs args
+  args' <- argsToVHDLExprs args
   wrap dst func args'
 
-eitherCoreOrExprArgs :: [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.Expr]
-eitherCoreOrExprArgs args = mapM (Either.either ((MonadState.lift tsType) . varToVHDLExpr . exprToVar) return) args
+-- | Turn the all lefts into VHDL Expressions.
+argsToVHDLExprs :: [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.Expr]
+argsToVHDLExprs = mapM argToVHDLExpr
+
+argToVHDLExpr :: Either CoreSyn.CoreExpr AST.Expr -> TranslatorSession AST.Expr
+argToVHDLExpr (Left expr) = MonadState.lift tsType $ varToVHDLExpr (exprToVar expr)
+argToVHDLExpr (Right expr) = return expr
 
 -- A function to wrap a builder-like function that generates no component
 -- instantiations
@@ -773,7 +778,7 @@ genApplication dst f args = do
           -- Local binder that references a top level binding.  Generate a
           -- component instantiation.
           signature <- getEntity f
-          args' <- eitherCoreOrExprArgs args
+          args' <- argsToVHDLExprs args
           let entity_id = ent_id signature
           -- TODO: Using show here isn't really pretty, but we'll need some
           -- unique-ish value...
@@ -794,7 +799,7 @@ genApplication dst f args = do
           Left bndr -> do
             -- We have the bndr, so we can get at the type
             labels <- MonadState.lift tsType $ getFieldLabels (Var.varType bndr)
-            args' <- eitherCoreOrExprArgs args
+            args' <- argsToVHDLExprs args
             return $ (zipWith mkassign labels $ args', [])
             where
               mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm