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Add a simple four-bit shift register model.
author
Matthijs Kooijman
<m.kooijman@student.utwente.nl>
Wed, 18 Feb 2009 19:27:20 +0000
(20:27 +0100)
committer
Matthijs Kooijman
<m.kooijman@student.utwente.nl>
Wed, 18 Feb 2009 19:27:20 +0000
(20:27 +0100)
This model is already translatable to VHDL.
No differences found