Make vhdl generation and normalization lazy.

Make vhdl generation and normalization lazy.

Previously, first all function would be (recursively) normalized, and then
VHDL would be generated. Now, functions are normalized when needed, and
recursion is done while generating VHDL (so we know exactly which
components we are instantiating).

This disables the testbench and TFVec constructor for now, I'll fix that
in the next commits.

This also moves some code around, to prevent loops between Generate and
VHDL (again...).

The VHDLSession and NormalizeSession have been removed, and replaced with
the (previously unused) TranslatorSession. There are a few backward
compatibility aliases in place, so the next commit will probably remove
these and do a bunch of trivial replaces all over the code.