Make vhdl generation and normalization lazy.

[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL / VHDLTypes.hs

diff --git a/cλash/CLasH/VHDL/VHDLTypes.hs b/cλash/CLasH/VHDL/VHDLTypes.hs
index 52adab7f944dfbeb8b164ed0983eda67a6216053..64fb7ab10bd8d063a9954997946e3e34bfbcb5cb 100644 (file)
--- a/cλash/CLasH/VHDL/VHDLTypes.hs
+++ b/cλash/CLasH/VHDL/VHDLTypes.hs
@@ -11,8 +11,6 @@ import Data.Accessor
 import qualified Data.Accessor.Template
 
 -- GHC API imports
-import qualified Type
-import qualified CoreSyn
 import qualified HscTypes
 
 -- ForSyDe imports
@@ -29,75 +27,10 @@ type Port = (AST.VHDLId, AST.TypeMark)
 data Entity = Entity { 
   ent_id     :: AST.VHDLId,           -- The id of the entity
   ent_args   :: [Port],      -- A mapping of each function argument to port names
-  ent_res    :: Port         -- A mapping of the function result to port names
+  ent_res    :: Port,         -- A mapping of the function result to port names
+  ent_dec    :: AST.EntityDec -- ^ The complete entity declaration
 } deriving (Show);
 
--- A orderable equivalent of CoreSyn's Type for use as a map key
-newtype OrdType = OrdType { getType :: Type.Type }
-instance Eq OrdType where
-  (OrdType a) == (OrdType b) = Type.tcEqType a b
-instance Ord OrdType where
-  compare (OrdType a) (OrdType b) = Type.tcCmpType a b
-
-data HType = StdType OrdType |
-             ADTType String [HType] |
-             VecType Int HType |
-             SizedWType Int |
-             RangedWType Int |
-             SizedIType Int |
-             BuiltinType String
-  deriving (Eq, Ord)
-
--- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map HType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
-
--- A map of a vector Core element type and function name to the coressponding
--- VHDLId of the function and the function body.
-type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
-
--- A map of a Haskell function to a hardware signature
-type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
-
-type TfpIntMap = Map.Map OrdType Int
-
-data TypeState = TypeState {
-  -- | A map of Core type -> VHDL Type
-  vsTypes_      :: TypeMap,
-  -- | A list of type declarations
-  vsTypeDecls_  :: [AST.PackageDecItem],
-  -- | A map of vector Core type -> VHDL type function
-  vsTypeFuns_   :: TypeFunMap,
-  vsTfpInts_    :: TfpIntMap,
-  vsHscEnv_     :: HscTypes.HscEnv
-}
--- Derive accessors
-$( Data.Accessor.Template.deriveAccessors ''TypeState )
--- Define a session
-type TypeSession = State.State TypeState
-
-data VHDLState = VHDLState {
-  -- | A subtype with typing info
-  vsType_       :: TypeState,
-  -- | A map of HsFunction -> hardware signature (entity name, port names,
-  --   etc.)
-  vsSignatures_ :: SignatureMap
-}
-
--- Derive accessors
-$( Data.Accessor.Template.deriveAccessors ''VHDLState )
-
--- | The state containing a VHDL Session
-type VHDLSession = State.State VHDLState
-
--- A function that generates VHDL for a builtin function
-type BuiltinBuilder = 
-  (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
-  -> CoreSyn.CoreBndr -- ^ The function called
-  -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
-                    --   dictionary arguments).
-  -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
-
--- A map of a builtin function to VHDL function builder 
-type NameTable = Map.Map String (Int, BuiltinBuilder )
+type Architecture = AST.ArchBody
 
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