Move the DesignFile creation to VHDL.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 17 Feb 2009 14:52:57 +0000 (15:52 +0100)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 17 Feb 2009 14:52:57 +0000 (15:52 +0100)
commite73057cb92295256ab62810771da8e723f4a8223
tree7ef65e4a1919a61ebe441d2f2b8db16d4c81d416
parent157dae90bdd7c45613c6ad6185383a1137b2323f
Move the DesignFile creation to VHDL.
Translator.hs
VHDL.hs