Let VHDL generate a typecast for SizedWord literals.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 14 Apr 2009 09:51:58 +0000 (11:51 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Tue, 14 Apr 2009 09:51:58 +0000 (11:51 +0200)
commit6f6ac4641e210ded85e42fdcceb316bd0ed64d13
treedad716d6c5ca46165ab378398ce245f3b8043ed7
parent5e5a75ab40e00110d5169b6713a7786978d91c04
Let VHDL generate a typecast for SizedWord literals.
Flatten.hs