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(parent: e90120f) | patch
Make output ports optional.
authorMatthijs Kooijman <m.kooijman@student.utwente.nl>
Wed, 12 Aug 2009 10:19:27 +0000 (12:19 +0200)
committerMatthijs Kooijman <m.kooijman@student.utwente.nl>
Wed, 12 Aug 2009 10:19:27 +0000 (12:19 +0200)
commit66ef5bd26b2c02cb12e702c60668294fd80ea8c2
treef2a42daf8ddb5285382ed7d567dcc59a24d2c849tree | snapshot
parente90120ffb6999ad931a06fd6c0a3b071408d5945commit | diff
Make output ports optional.

This makes the output port in an Entity of the Maybe Port type, so we can
leave out the output port (for example when its type is empty). This makes
the code a bit more robus in the face of empty types.
cλash/CLasH/VHDL/Generate.hs diff | blob | history
cλash/CLasH/VHDL/Testbench.hs diff | blob | history
cλash/CLasH/VHDL/VHDLTools.hs diff | blob | history
cλash/CLasH/VHDL/VHDLTypes.hs diff | blob | history
The Cλash compiler