Make output ports optional.

[matthijs/master-project/cλash.git] / cλash / CLasH / VHDL / VHDLTypes.hs

diff --git a/cλash/CLasH/VHDL/VHDLTypes.hs b/cλash/CLasH/VHDL/VHDLTypes.hs
index fbdf4d72932b37daedca11af577526226dec7de8..e95a0c6eac6af1bbd8fe948fc8e769079f82d2e4 100644 (file)
--- a/cλash/CLasH/VHDL/VHDLTypes.hs
+++ b/cλash/CLasH/VHDL/VHDLTypes.hs
@@ -27,7 +27,7 @@ type Port = (AST.VHDLId, AST.TypeMark)
 data Entity = Entity { 
   ent_id     :: AST.VHDLId, -- ^ The id of the entity
   ent_args   :: [Port], -- ^ A port for each non-empty function argument
-  ent_res    :: Port, -- ^ The output port
+  ent_res    :: Maybe Port, -- ^ The output port
   ent_dec    :: AST.EntityDec -- ^ The complete entity declaration
 } deriving (Show);