+--
-- Functions to create a VHDL testbench from a list of test input.
--
module CLasH.VHDL.Testbench where
-> Entity
createTestbenchEntity bndr = entity
where
- vhdl_id = mkVHDLBasicId $ varToString bndr
+ vhdl_id = mkVHDLBasicId "testbench"
-- Create an AST entity declaration with no ports
ent_decl = AST.EntityDec vhdl_id []
-- Create a signature with no input and no output ports
let finalIDecs = iDecs ++
[AST.SigDec clockId std_logicTM (Just $ AST.PrimLit "'0'"),
AST.SigDec resetId std_logicTM (Just $ AST.PrimLit "'0'")]
- portmaps <- mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
+ let portmaps = mkAssocElems (map idToVHDLExpr iIds) (AST.NSimple oId) signature
let mIns = mkComponentInst "totest" entId portmaps
(stimuliAssigns, stimuliDecs, cycles, used) <- createStimuliAssigns mCycles stimuli (head iIds)
let finalAssigns = (AST.CSSASm (AST.NSimple resetId AST.:<==:
AST.ConWforms []
- (AST.Wform [AST.WformElem (AST.PrimLit "'1'") (Just $ AST.PrimLit "3 ns")])
+ (AST.Wform [AST.WformElem (AST.PrimLit "'0'") (Just $ AST.PrimLit "0 ns"), AST.WformElem (AST.PrimLit "'1'") (Just $ AST.PrimLit "3 ns")])
Nothing)) : stimuliAssigns
let clkProc = createClkProc
let arch = AST.ArchBody
createStimulans expr cycl = do
-- There must be a let at top level
- (CoreSyn.Let (CoreSyn.Rec binds) (Var res)) <- normalizeExpr ("test input #" ++ show cycl) expr
+ expr <- normalizeExpr ("test input #" ++ show cycl) expr
+ -- Split the normalized expression. It can't have a function type, so match
+ -- an empty list of argument binders
+ let ([], binds, res) = splitNormalized expr
(stimulansbindss, useds) <- unzipM $ Monad.mapM mkConcSm binds
sig_dec_maybes <- mapM (mkSigDec . fst) (filter ((/=res).fst) binds)
let sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)