Allow explicit empty VHDL types using Maybe.

[matthijs/master-project/cλash.git] / cλash / CLasH / Translator / TranslatorTypes.hs

diff --git a/cλash/CLasH/Translator/TranslatorTypes.hs b/cλash/CLasH/Translator/TranslatorTypes.hs
index 257c543e2f9f799980f8035ab89bb7ac4b009050..075871ac59e9f347b5268a1dd409cec700d3ba48 100644 (file)
--- a/cλash/CLasH/Translator/TranslatorTypes.hs
+++ b/cλash/CLasH/Translator/TranslatorTypes.hs
@@ -54,8 +54,9 @@ data HType = StdType OrdType |
              BuiltinType String
   deriving (Eq, Ord)
 
--- A map of a Core type to the corresponding type name
-type TypeMap = Map.Map HType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
+-- A map of a Core type to the corresponding type name, or Nothing when the
+-- type would be empty.
+type TypeMap = Map.Map HType (Maybe (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn))
 
 -- A map of a vector Core element type and function name to the coressponding
 -- VHDLId of the function and the function body.