Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project

[matthijs/master-project/cλash.git] / VHDLTypes.hs

diff --git a/VHDLTypes.hs b/VHDLTypes.hs
index 59da9c17341dfc1d63f70f89673159071848055a..79d7675f68a48f3663782d0d6c6465d90c0ef871 100644 (file)
--- a/VHDLTypes.hs
+++ b/VHDLTypes.hs
@@ -48,8 +48,9 @@ type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
 -- A map of Elem types to the corresponding VHDL Id for the Vector
 type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
 
--- A map of a vector Core type to the coressponding VHDL functions
-type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
+-- A map of a vector Core element type and function name to the coressponding
+-- VHDLId of the function and the function body.
+type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
 
 -- A map of a Haskell function to a hardware signature
 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
@@ -75,9 +76,15 @@ type VHDLSession = State.State VHDLState
 -- | A substate containing just the types
 type TypeState = State.State TypeMap
 
-type Builder = Either ([AST.Expr] -> AST.Expr) (Entity -> [CoreSyn.CoreBndr] -> AST.GenerateSm)
+-- A function that generates VHDL for a builtin function
+type BuiltinBuilder = 
+  CoreSyn.CoreBndr -- ^ The destination value
+  -> CoreSyn.CoreBndr -- ^ The function called
+  -> [CoreSyn.CoreExpr] -- ^ The value arguments passed (excluding type and
+                        --   dictionary arguments).
+  -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
 
 -- A map of a builtin function to VHDL function builder 
-type NameTable = Map.Map String (Int, Builder )
+type NameTable = Map.Map String (Int, BuiltinBuilder )
 
 -- vim: set ts=8 sw=2 sts=2 expandtab: