Move the DesignFile creation to VHDL.

[matthijs/master-project/cλash.git] / VHDL.hs

diff --git a/VHDL.hs b/VHDL.hs
index ef89c4a6dbcda9a592419b5e79aa40786651ee2b..5d57bb574c98fe55f51e041306e42ccabfcf6950 100644 (file)
--- a/VHDL.hs
+++ b/VHDL.hs
@@ -20,6 +20,16 @@ import FlattenTypes
 import TranslatorTypes
 import Pretty
 
+getDesignFile :: VHDLState AST.DesignFile
+getDesignFile = do
+  -- Extract the library units generated from all the functions in the
+  -- session.
+  funcs <- getFuncs
+  let units = concat $ map getLibraryUnits funcs
+  return $ AST.DesignFile 
+    []
+    units
+  
 -- | Create an entity for a given function
 createEntity ::
   HsFunction        -- | The function signature
@@ -58,7 +68,7 @@ createEntity hsfunc fdata =
           (sigName info)
         ty = sigTy info
 
--- | Create the VHDL AST for an entity
+  -- | Create the VHDL AST for an entity
 createEntityAST ::
   HsFunction            -- | The signature of the function we're working with
   -> [VHDLSignalMap]    -- | The entity's arguments
@@ -71,9 +81,16 @@ createEntityAST hsfunc args res =
     vhdl_id = mkEntityId hsfunc
     ports = concatMap (mapToPorts AST.In) args
             ++ mapToPorts AST.Out res
+            ++ clk_port
     mapToPorts :: AST.Mode -> VHDLSignalMap -> [AST.IfaceSigDec] 
     mapToPorts mode m =
       map (mkIfaceSigDec mode) (Foldable.toList m)
+    -- Add a clk port if we have state
+    clk_port = if hasState hsfunc
+      then
+        [AST.IfaceSigDec (mkVHDLId "clk") AST.In VHDL.std_logic_ty]
+      else
+        []
 
 -- | Create a port declaration
 mkIfaceSigDec ::
@@ -230,6 +247,10 @@ getLibraryUnits (hsfunc, fdata) =
 bit_ty :: AST.TypeMark
 bit_ty = AST.unsafeVHDLBasicId "Bit"
 
+-- | The VHDL std_logic
+std_logic_ty :: AST.TypeMark
+std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
+
 -- Translate a Haskell type to a VHDL type
 vhdl_ty :: Type.Type -> AST.TypeMark
 vhdl_ty ty = Maybe.fromMaybe