Add a simple four-bit shift register model.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 53befc228e6ef947107b72141d9cb7c713fd5606..cf2fb966876c5ffd612d00360dfe772a4adf2110 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -45,7 +45,7 @@ main = do
   -- Load the module
   core <- loadModule "Adders.hs"
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["sfull_adder"]
+  vhdl <- moduleToVHDL core ["shifter"]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"