Add a simple four-bit shift register model.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index 3cf456e0ea6118145796430b19d0487c24f630d9..cf2fb966876c5ffd612d00360dfe772a4adf2110 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -45,10 +45,19 @@ main = do
   -- Load the module
   core <- loadModule "Adders.hs"
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["sfull_adder"]
+  vhdl <- moduleToVHDL core ["shifter"]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
 
+-- | Show the core structure of the given binds in the given file.
+listBind :: String -> String -> IO ()
+listBind filename name = do
+  core <- loadModule filename
+  let binds = findBinds core [name]
+  putStr "\n"
+  putStr $ prettyShow binds
+  putStr "\n\n"
+
 -- | Translate the binds with the given names from the given core module to
 --   VHDL
 moduleToVHDL :: HscTypes.CoreModule -> [String] -> IO AST.DesignFile