Make register_bank work, with a bunch of changes.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index ddd09fc340da9a401a24e1399c797de60c238234..1a753c2d52b592af9dbc50811bf90b5330f35702 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -42,7 +42,7 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
-  makeVHDL "Alu.hs" "salu"
+  makeVHDL "Alu.hs" "register_bank"
 
 makeVHDL :: String -> String -> IO ()
 makeVHDL filename name = do
@@ -60,6 +60,7 @@ listBind filename name = do
   let binds = findBinds core [name]
   putStr "\n"
   putStr $ prettyShow binds
+  putStr $ showSDoc $ ppr binds
   putStr "\n\n"
 
 -- | Translate the binds with the given names from the given core module to