Make register_bank work, with a bunch of changes.

[matthijs/master-project/cλash.git] / Translator.hs

diff --git a/Translator.hs b/Translator.hs
index c16406be3aef2781484251c56a21d3e5fb394f54..1a753c2d52b592af9dbc50811bf90b5330f35702 100644 (file)
--- a/Translator.hs
+++ b/Translator.hs
@@ -42,10 +42,14 @@ import VHDLTypes
 import qualified VHDL
 
 main = do
+  makeVHDL "Alu.hs" "register_bank"
+
+makeVHDL :: String -> String -> IO ()
+makeVHDL filename name = do
   -- Load the module
-  core <- loadModule "Adders.hs"
+  core <- loadModule filename
   -- Translate to VHDL
-  vhdl <- moduleToVHDL core ["dff"]
+  vhdl <- moduleToVHDL core [name]
   -- Write VHDL to file
   writeVHDL vhdl "../vhdl/vhdl/output.vhdl"
 
@@ -56,6 +60,7 @@ listBind filename name = do
   let binds = findBinds core [name]
   putStr "\n"
   putStr $ prettyShow binds
+  putStr $ showSDoc $ ppr binds
   putStr "\n\n"
 
 -- | Translate the binds with the given names from the given core module to