Make register_bank work, with a bunch of changes.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index 183125cc65761869c7221e8bb4b5c75c641e38f4..679d7ae4261c1b24ff3f4b61b9f92cab3af2ed8c 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -1,13 +1,16 @@
 module Pretty (prettyShow) where
 
 import qualified Data.Map as Map
+import qualified Var
 import qualified CoreSyn
+import qualified TypeRep
 import qualified Module
 import qualified HscTypes
 import Text.PrettyPrint.HughesPJClass
 import Outputable ( showSDoc, ppr, Outputable, OutputableBndr)
 
 import qualified ForSyDe.Backend.Ppr
+import qualified ForSyDe.Backend.VHDL.Ppr
 import qualified ForSyDe.Backend.VHDL.AST as AST
 
 import HsValueMap
@@ -33,7 +36,7 @@ instance Pretty x => Pretty (HsValueMap x) where
 
 instance Pretty HsValueUse where
   pPrint Port            = char 'P'
-  pPrint (State n)       = char 'C' <> int n
+  pPrint (State n)       = char 'S' <> int n
   pPrint (HighOrder _ _) = text "Higher Order"
 
 instance Pretty FlatFunction where
@@ -48,8 +51,21 @@ instance Pretty FlatFunction where
 instance Pretty SigDef where
   pPrint (FApp func args res) =
     pPrint func <> text " : " <> pPrint args <> text " -> " <> pPrint res
-  pPrint (CondDef _ _ _ _) = text "TODO"
-  pPrint (UncondDef src dst) = text "TODO"
+  pPrint (CondDef cond true false res) = 
+    pPrint cond <> text " ? " <> pPrint true <> text " : " <> pPrint false <> text " -> " <> pPrint res
+  pPrint (UncondDef src dst) =
+    ppsrc src <> text " -> " <> pPrint dst
+    where
+      ppsrc (Left id) = pPrint id
+      ppsrc (Right expr) = pPrint expr
+
+instance Pretty SignalExpr where
+  pPrint (EqLit id lit) =
+    parens $ pPrint id <> text " = " <> text lit
+  pPrint (Literal lit) =
+    text lit
+  pPrint (Eq a b) =
+    parens $ pPrint a <> text " = " <> pPrint b
 
 instance Pretty SignalInfo where
   pPrint (SignalInfo name use ty) =
@@ -99,7 +115,7 @@ instance Pretty Entity where
       ppdecl Nothing = text "VHDL entity not present"
       ppdecl (Just _) = text "VHDL entity present"
 
-instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
+instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Bind b) where
   pPrint (CoreSyn.NonRec b expr) =
     text "NonRec: " $$ nest 10 (prettyBind (b, expr))
   pPrint (CoreSyn.Rec binds) =
@@ -108,9 +124,21 @@ instance (OutputableBndr b) => Pretty (CoreSyn.Bind b) where
 instance Pretty AST.VHDLId where
   pPrint id = ForSyDe.Backend.Ppr.ppr id
 
-prettyBind :: (Outputable b, Outputable e) => (b, e) -> Doc
+prettyBind :: (Show b, Show e) => (b, e) -> Doc
 prettyBind (b, expr) =
   text b' <> text " = " <> text expr'
   where
-    b' = showSDoc $ ppr b
-    expr' = showSDoc $ ppr expr
+    b' = show b
+    expr' = show expr
+
+-- Derive Show for core expressions and binders, so we can see the actual
+-- structure.
+deriving instance (Show b) => Show (CoreSyn.Expr b)
+deriving instance (Show b) => Show (CoreSyn.Bind b)
+
+-- Implement dummy shows for Note and Type, so we can at least use show on
+-- expressions.
+instance Show CoreSyn.Note where
+  show n = "<note>"
+instance Show TypeRep.Type where
+  show t = "_type:(" ++ (showSDoc $ ppr t) ++ ")"