Generate a VHDL architecture for each function.

[matthijs/master-project/cλash.git] / Pretty.hs

diff --git a/Pretty.hs b/Pretty.hs
index 3797fe2ad1e0f3a45b8a8094e39742b1fa3ac5bd..561cfb10d489c113f3a2b9d48527847c7d39eb9e 100644 (file)
--- a/Pretty.hs
+++ b/Pretty.hs
@@ -47,8 +47,8 @@ instance Pretty id => Pretty (CondDef id) where
   pPrint _ = text "TODO"
 
 instance Pretty SignalInfo where
-  pPrint (SignalInfo Nothing) = empty
-  pPrint (SignalInfo (Just name)) = text ":" <> text name
+  pPrint (SignalInfo Nothing ty) = empty
+  pPrint (SignalInfo (Just name) ty) = text ":" <> text name
 
 instance Pretty VHDLSession where
   pPrint (VHDLSession mod nameCount funcs) =
@@ -56,13 +56,16 @@ instance Pretty VHDLSession where
     $+$ text "NameCount: " $$ nest 15 (int nameCount)
     $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
     where
-      ppfunc (hsfunc, (FuncData flatfunc entity)) =
+      ppfunc (hsfunc, (FuncData flatfunc entity arch)) =
         pPrint hsfunc $+$ (text "Flattened: " $$ nest 15 (ppffunc flatfunc))
         $+$ (text "Entity") $$ nest 15 (ppent entity)
+        $+$ pparch arch
       ppffunc (Just f) = pPrint f
       ppffunc Nothing  = text "Nothing"
       ppent (Just e)   = pPrint e
       ppent Nothing    = text "Nothing"
+      pparch Nothing = text "VHDL architecture not present"
+      pparch (Just _) = text "VHDL architecture present"
       modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
 
 instance Pretty Entity where