- \item We designed a matrix reduction circuit\pause
- \item Simulation results in Haskell match VHDL simulation results
- \item Synthesis completes without errors or warnings
- \item It runs at half the speed of a hand-coded VHDL design
+ \item We designed a reduction circuit in \clash{}\pause
+ \item Simulation results in Haskell match VHDL simulation results\pause
+ \item Synthesis completes without errors or warnings\pause
+ \item For the same Virtex-4 FPGA: \pause
+ \begin{itemize}
+ \item Hand coded VHDL design runs at 200 MHz\pause
+ \item \clash{} design runs at around 85* MHz
+ \end{itemize}