Added images

[matthijs/master-project/haskell-symposium-talk.git] / reducer.lhs

diff --git a/reducer.lhs b/reducer.lhs
index f71d1f62a270dfd15bdf702ae43175bbddc5e120..03c688c520ac496f98c8657ca05968c9c96658d0 100644 (file)
--- a/reducer.lhs
+++ b/reducer.lhs
@@ -2,15 +2,28 @@
 \frame{
 \frametitle{More than just toys}
 \pause
 \frame{
 \frametitle{More than just toys}
 \pause

+\begin{columns}[l]
+\column{0.5\textwidth}
+\begin{figure}
+\includegraphics<2->[width=5.5cm]{reducer}
+\end{figure}
+\column{0.5\textwidth}

 \begin{itemize}
 \begin{itemize}

-  \item We designed a matrix reduction circuit\pause
+  \item We implemented a reduction circuit in \clash{}\pause

   \item Simulation results in Haskell match VHDL simulation results\pause
   \item Synthesis completes without errors or warnings\pause
   \item Simulation results in Haskell match VHDL simulation results\pause
   \item Synthesis completes without errors or warnings\pause

-  \item It runs at half the speed of a hand-coded VHDL design
+  \item Around half speed of handcoded and optimized VHDL

 \end{itemize}
 \end{itemize}

+\end{columns}

 }\note[itemize]{
 \item Toys like the poly cpu one are good to give a quick demo
 \item But we used \clash{} to design 'real' hardware
 \item Reduction circuit sums the numbers in a row of a (sparse) matrix
 }\note[itemize]{
 \item Toys like the poly cpu one are good to give a quick demo
 \item But we used \clash{} to design 'real' hardware
 \item Reduction circuit sums the numbers in a row of a (sparse) matrix

-\item Half speed is nice, considering we don't optimize for speed
-}
\ No newline at end of file
+\item Nice speed considering we don't optimize for it (only single example!)
+}
+
+% \begin{frame}[plain] 
+%    \begin{centering} 
+%       \includegraphics[height=\paperheight]{reducerschematic.png} 
+%       \end{centering} 
+% \end{frame}